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From: | Bowen Hu |
Subject: | [Discuss-gnuradio] [GSoC19] gr-verilog master branch merged |
Date: | Thu, 22 Aug 2019 14:01:13 +0000 |
Hi all,
The gr-verilog is an OOT module for GNU Radio integrating Verilog simulation feature. This is the work of GSoC19.
GSoC19 is nearing the end, and I have merged the axi-general branch to master branch.
You can find more information in the repository here (https://github.com/B0WEN-HU/gr-verilog).
Please feel free to try this OOT module.
Best regards,
Bowen
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