>From 6da0b3ed7d1794bc640326c6f46cb27ca0275b08 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=BCdiger=20Sonderfeld?=
Date: Wed, 23 May 2012 14:28:00 +0200
Subject: [PATCH 1/2] progmodes/vhdl-mode.el: Backported changes from 3.33.
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To: address@hidden
See
http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html#release-notes-3.33
Among the changes are
* Support for ghdl (free vhdl compiler). Now default
* Add/update support for VHDL-AMS packages.
* Update to VHDL'02 standard
...
I tried to be very careful not to overwrite any non-upstream changes
that were made to vhdl-mode.
Signed-off-by: RĂ¼diger Sonderfeld
---
lisp/progmodes/vhdl-mode.el | 1303 +++++++++++++++++++++++++++++--------------
1 file changed, 893 insertions(+), 410 deletions(-)
diff --git a/lisp/progmodes/vhdl-mode.el b/lisp/progmodes/vhdl-mode.el
index 9b7ee5d..27215de 100644
--- a/lisp/progmodes/vhdl-mode.el
+++ b/lisp/progmodes/vhdl-mode.el
@@ -13,10 +13,10 @@
;; filed in the Emacs bug reporting system against this file, a copy
;; of the bug report be sent to the maintainer's email address.
-(defconst vhdl-version "3.33.6"
+(defconst vhdl-version "3.33.28"
"VHDL Mode version number.")
-(defconst vhdl-time-stamp "2005-08-30"
+(defconst vhdl-time-stamp "2010-09-22"
"VHDL Mode time stamp for last update.")
;; This file is part of GNU Emacs.
@@ -72,13 +72,13 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Emacs Versions
-;; supported: GNU Emacs 20.X/21.X/22.X, XEmacs 20.X/21.X
-;; tested on: GNU Emacs 20.4, XEmacs 21.1 (marginally)
+;; supported: GNU Emacs 20.X/21.X/22.X,23.X, XEmacs 20.X/21.X
+;; tested on: GNU Emacs 20.4/21.3/22.1,23.X, XEmacs 21.1 (marginally)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Installation
-;; Prerequisites: GNU Emacs 20.X/21.X/22.X, XEmacs 20.X/21.X.
+;; Prerequisites: GNU Emacs 20.X/21.X/22.X/23.X, XEmacs 20.X/21.X.
;; Put `vhdl-mode.el' into the `site-lisp' directory of your Emacs installation
;; or into an arbitrary directory that is added to the load path by the
@@ -93,7 +93,7 @@
;; Add the following lines to the `site-start.el' file in the `site-lisp'
;; directory of your Emacs installation or to your Emacs start-up file `.emacs'
-;; (not required in Emacs 20.X):
+;; (not required in Emacs 20 and higher):
;; (autoload 'vhdl-mode "vhdl-mode" "VHDL Mode" t)
;; (setq auto-mode-alist (cons '("\\.vhdl?\\'" . vhdl-mode) auto-mode-alist))
@@ -184,7 +184,7 @@ Examples:
\".*\" \"\" inserts empty string")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; User variables
+;; User variables (customization options)
(defgroup vhdl nil
"Customizations for VHDL Mode."
@@ -197,6 +197,21 @@ Examples:
"Customizations for modes."
:group 'vhdl)
+(defcustom vhdl-electric-mode t
+ "Non-nil enables electrification (automatic template generation).
+If nil, template generators can still be invoked through key bindings and
+menu. Is indicated in the modeline by \"/e\" after the mode name and can be
+toggled by `\\[vhdl-electric-mode]'."
+ :type 'boolean
+ :group 'vhdl-mode)
+
+(defcustom vhdl-stutter-mode t
+ "Non-nil enables stuttering.
+Is indicated in the modeline by \"/s\" after the mode name and can be toggled
+by `\\[vhdl-stutter-mode]'."
+ :type 'boolean
+ :group 'vhdl-mode)
+
(defcustom vhdl-indent-tabs-mode nil
"Non-nil means indentation can insert tabs.
Overrides local variable `indent-tabs-mode'."
@@ -210,6 +225,17 @@ Overrides local variable `indent-tabs-mode'."
(defcustom vhdl-compiler-alist
'(
+ ("ADVance MS" "vacom" "-work \\1" "make" "-f \\1"
+ nil "valib \\1; vamap \\2 \\1" "./" "work/" "Makefile" "adms"
+ ("\\s-\\([0-9]+\\):" 0 1 0) ("Compiling file \\(.+\\)" 1)
+ ("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif"
+ "PACK/\\1.vif" "BODY/\\1.vif" upcase))
+ ;; Aldec
+ ;; COMP96 ERROR COMP96_0078: "Unknown identifier "Addr_Bits"." "" 40 30
+ ("Aldec" "vcom" "-93 -work \\1" "make" "-f \\1"
+ nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "aldec"
+ (".+?[ \t]+\\(?:ERROR\\)[^:]+:.+?\\(?:.+\"\\(.+?\\)\"[ \t]+\\([0-9]+\\)\\)" 1 2 0) ("" 0)
+ nil)
;; Cadence Leapfrog: cv -file test.vhd
;; duluth: *E,430 (test.vhd,13): identifier (POSITIV) is not declared
("Cadence Leapfrog" "cv" "-work \\1 -file" "make" "-f \\1"
@@ -225,6 +251,12 @@ Overrides local variable `indent-tabs-mode'."
("ncvhdl_p: \\*E,\\w+ (\\(.+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3) ("" 0)
("\\1/entity/pc.db" "\\2/\\1/pc.db" "\\1/configuration/pc.db"
"\\1/package/pc.db" "\\1/body/pc.db" downcase))
+ ;; ghdl vhdl: ghdl test.vhd
+ ("GHDL" "ghdl" "-i --workdir=\\1 --ieee=synopsys -fexplicit " "make" "-f \\1"
+ nil "mkdir \\1" "./" "work/" "Makefile" "ghdl"
+ ("ghdl_p: \\*E,\\w+ (\\(.+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3) ("" 0)
+ ("\\1/entity" "\\2/\\1" "\\1/configuration"
+ "\\1/package" "\\1/body" downcase))
;; Ikos Voyager: analyze test.vhd
;; analyze test.vhd
;; E L4/C5: this library unit is inaccessible
@@ -236,10 +268,11 @@ Overrides local variable `indent-tabs-mode'."
;; ModelSim, Model Technology: vcom test.vhd
;; ERROR: test.vhd(14): Unknown identifier: positiv
;; WARNING[2]: test.vhd(85): Possible infinite loop
+ ;; ** Warning: [4] ../src/emacsvsim.vhd(43): An abstract ...
;; ** Error: adder.vhd(190): Unknown identifier: ctl_numb
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
- ("\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*: \\(.+\\)(\\([0-9]+\\)):" 2 3 0) ("" 0)
+ ("\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\[[0-9]+\]\\)? \\(.+\\)(\\([0-9]+\\)):" 3 4 0) ("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; ProVHDL, Synopsys LEDA: provhdl -w work -f test.vhd
@@ -321,6 +354,12 @@ Overrides local variable `indent-tabs-mode'."
("\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" 0 1 0)
("^ *Compiling \"\\(.+\\)\" " 1)
nil)
+ ;; Xilinx XST:
+ ;; ERROR:HDLParsers:164 - "test.vhd" Line 3. parse error
+ ("Xilinx XST" "xflow" "" "make" "-f \\1"
+ nil "mkdir \\1" "./" "work/" "Makefile" "xilinx"
+ ("^ERROR:HDLParsers:[0-9]+ - \"\\(.+\\)\" Line \\([0-9]+\\)\." 1 2 0) ("" 0)
+ nil)
)
"List of available VHDL compilers and their properties.
Each list entry specifies the following items for a compiler:
@@ -428,7 +467,7 @@ NOTE: Activate new error and file message regexps and reflect the new setting
(vhdl-custom-set variable value 'vhdl-update-mode-menu))
:group 'vhdl-compile)
-(defcustom vhdl-compiler "ModelSim"
+(defcustom vhdl-compiler "GHDL"
"Specifies the VHDL compiler to be used for syntax analysis.
Select a compiler name from the ones defined in option `vhdl-compiler-alist'."
:type (let ((alist vhdl-compiler-alist) list)
@@ -450,6 +489,17 @@ NOTE: Activate the new setting by restarting Emacs."
:type 'boolean
:group 'vhdl-compile)
+(defcustom vhdl-makefile-default-targets '("all" "clean" "library")
+ "List of default target names in Makefiles.
+Automatically generated Makefiles include three default targets to compile
+the entire design, clean the entire design and to create the design library.
+This option allows to change the names of these targets to avoid conflicts
+with other user Makefiles."
+ :type '(list (string :tag "Compile entire design")
+ (string :tag "Clean entire design ")
+ (string :tag "Create design library"))
+ :group 'vhdl-compile)
+
(defcustom vhdl-makefile-generation-hook nil
"Functions to run at the end of Makefile generation.
Allows to insert user specific parts into a Makefile.
@@ -647,11 +697,11 @@ A project setup file can be obtained by exporting a project (see menu).
:group 'vhdl-port
:group 'vhdl-compose)
-(defcustom vhdl-standard '(87 nil)
+(defcustom vhdl-standard '(93 nil)
"VHDL standards used.
Basic standard:
VHDL'87 : IEEE Std 1076-1987
- VHDL'93 : IEEE Std 1076-1993
+ VHDL'93/02 : IEEE Std 1076-1993/2002
Additional standards:
VHDL-AMS : IEEE Std 1076.1 (analog-mixed-signal)
Math packages: IEEE Std 1076.2 (`math_real', `math_complex')
@@ -660,7 +710,7 @@ NOTE: Activate the new setting in a VHDL buffer by using the menu entry
\"Activate Options\"."
:type '(list (choice :tag "Basic standard"
(const :tag "VHDL'87" 87)
- (const :tag "VHDL'93" 93))
+ (const :tag "VHDL'93/02" 93))
(set :tag "Additional standards" :indent 2
(const :tag "VHDL-AMS" ams)
(const :tag "Math packages" math)))
@@ -730,6 +780,14 @@ This is done when expanded."
(const :tag "Always" always))
:group 'vhdl-style)
+(defcustom vhdl-array-index-record-field-in-sensitivity-list t
+ "Non-nil means include array indices / record fields in sensitivity list.
+If a signal read in a process is a record field or pointed to by an array
+index, the record field or array index is included with the record name in
+the sensitivity list (e.g. \"in1(0)\", \"in2.f0\").
+Otherwise, only the record name is included (e.g. \"in1\", \"in2\")."
+ :type 'boolean
+ :group 'vhdl-style)
(defgroup vhdl-naming nil
"Customizations for naming conventions."
@@ -916,7 +974,8 @@ if the header needs to be version controlled.
The following keywords for template generation are supported:
: replaced by the name of the buffer
: replaced by the user name and email address
- \(`user-full-name', `mail-host-address', `user-mail-address')
+ \(`user-full-name',`mail-host-address', `user-mail-address')
+ : replaced by the user full name (`user-full-name')
: replaced by user login name (`user-login-name')
: replaced by contents of option `vhdl-company-name'
: replaced by the current date
@@ -999,11 +1058,12 @@ NOTE: Activate the new setting in a VHDL buffer by using the menu entry
"Customizations for sequential processes."
:group 'vhdl-template)
-(defcustom vhdl-reset-kind 'async
+(defcustom vhdl-reset-kind 'async
"Specifies which kind of reset to use in sequential processes."
:type '(choice (const :tag "None" none)
(const :tag "Synchronous" sync)
- (const :tag "Asynchronous" async))
+ (const :tag "Asynchronous" async)
+ (const :tag "Query" query))
:group 'vhdl-sequential-process)
(defcustom vhdl-reset-active-high nil
@@ -1563,22 +1623,25 @@ NOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu
:group 'vhdl-highlight)
(defcustom vhdl-special-syntax-alist
- '(("generic/constant" "\\w+_[cg]" "Gold3" "BurlyWood1")
- ("type" "\\w+_t" "ForestGreen" "PaleGreen")
- ("variable" "\\w+_v" "Grey50" "Grey80"))
+ '(("generic/constant" "\\<\\w+_[cg]\\>" "Gold3" "BurlyWood1" nil)
+ ("type" "\\<\\w+_t\\>" "ForestGreen" "PaleGreen" nil)
+ ("variable" "\\<\\w+_v\\>" "Grey50" "Grey80" nil))
"List of special syntax to be highlighted.
If option `vhdl-highlight-special-words' is non-nil, words with the specified
syntax (as regular expression) are highlighted in the corresponding color.
Name : string of words and spaces
Regexp : regular expression describing word syntax
- (e.g. \"\\\w+_c\" matches word with suffix \"_c\")
+ (e.g. \"\\\\=\<\\\w+_c\\\\=\>\" matches word with suffix \"_c\")
+ expression must start with \"\\\\=\<\" and end with \"\\\\=\>\"
+ if only whole words should be matched (no substrings)
Color (light): foreground color for light background
(matching color examples: Gold3, Grey50, LimeGreen, Tomato,
LightSeaGreen, DodgerBlue, Gold, PaleVioletRed)
Color (dark) : foreground color for dark background
(matching color examples: BurlyWood1, Grey80, Green, Coral,
AquaMarine2, LightSkyBlue1, Yellow, PaleVioletRed1)
+ In comments : If non-nil, words are also highlighted inside comments
Can be used for visual support of naming conventions, such as highlighting
different kinds of signals (e.g. \"Clk50\", \"Rst_n\") or objects (e.g.
@@ -1593,7 +1656,8 @@ NOTE: Activate a changed regexp in a VHDL buffer by re-fontifying it (menu
(string :tag "Name ")
(regexp :tag "Regexp " "\\w+_")
(string :tag "Color (light)")
- (string :tag "Color (dark) ")))
+ (string :tag "Color (dark) ")
+ (boolean :tag "In comments ")))
:set (lambda (variable value)
(vhdl-custom-set variable value 'vhdl-font-lock-init))
:group 'vhdl-highlight)
@@ -1794,6 +1858,14 @@ useful in large files where syntax-based indentation gets very slow."
:type 'boolean
:group 'vhdl-misc)
+(defcustom vhdl-indent-comment-like-next-code-line t
+ "*Non-nil means comment lines are indented like the following code line.
+Otherwise, comment lines are indented like the preceding code line.
+Indenting comment lines like the following code line gives nicer indentation
+when comments precede the code that they refer to."
+ :type 'boolean
+ :group 'vhdl-misc)
+
(defcustom vhdl-word-completion-case-sensitive nil
"Non-nil means word completion using `TAB' is case sensitive.
That is, `TAB' completes words that start with the same letters and case.
@@ -1833,6 +1905,7 @@ NOTE: Activate the new setting in a VHDL buffer by using the menu entry
(custom-add-to-group 'vhdl-related 'paren-showing 'custom-group))
(custom-add-to-group 'vhdl-related 'ps-print 'custom-group)
(custom-add-to-group 'vhdl-related 'speedbar 'custom-group)
+(custom-add-to-group 'vhdl-related 'comment-style 'custom-variable)
(custom-add-to-group 'vhdl-related 'line-number-mode 'custom-variable)
(unless (featurep 'xemacs)
(custom-add-to-group 'vhdl-related 'transient-mark-mode 'custom-variable))
@@ -1841,6 +1914,15 @@ NOTE: Activate the new setting in a VHDL buffer by using the menu entry
(custom-add-to-group 'vhdl-related 'user-mail-address 'custom-variable)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Hidden user variables
+
+(defvar vhdl-compile-absolute-path nil
+ "If non-nil, use absolute instead of relative path for compiled files.")
+
+(defvar vhdl-comment-display-line-char ?-
+ "Character to use in comment display line.")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Internal variables
(defvar vhdl-menu-max-size 20
@@ -3270,9 +3352,6 @@ STRING are replaced by `-' and substrings are converted to lower case."
(list
(append
'("Package")
- (when (vhdl-standard-p 'math)
- '(["math_complex" vhdl-template-package-math-complex t]
- ["math_real" vhdl-template-package-math-real t]))
'(["numeric_bit" vhdl-template-package-numeric-bit t]
["numeric_std" vhdl-template-package-numeric-std t]
["std_logic_1164" vhdl-template-package-std-logic-1164 t]
@@ -3283,8 +3362,22 @@ STRING are replaced by `-' and substrings are converted to lower case."
["std_logic_unsigned" vhdl-template-package-std-logic-unsigned t]
["std_logic_misc" vhdl-template-package-std-logic-misc t]
["std_logic_textio" vhdl-template-package-std-logic-textio t]
- "--"
- ["Insert Package..." vhdl-template-insert-package
+ "--")
+ (when (vhdl-standard-p 'ams)
+ '(["fundamental_constants" vhdl-template-package-fundamental-constants t]
+ ["material_constants" vhdl-template-package-material-constants t]
+ ["energy_systems" vhdl-template-package-energy-systems t]
+ ["electrical_systems" vhdl-template-package-electrical-systems t]
+ ["mechanical_systems" vhdl-template-package-mechanical-systems t]
+ ["radiant_systems" vhdl-template-package-radiant-systems t]
+ ["thermal_systems" vhdl-template-package-thermal-systems t]
+ ["fluidic_systems" vhdl-template-package-fluidic-systems t]
+ "--"))
+ (when (vhdl-standard-p 'math)
+ '(["math_complex" vhdl-template-package-math-complex t]
+ ["math_real" vhdl-template-package-math-real t]
+ "--"))
+ '(["Insert Package..." vhdl-template-insert-package
:keys "C-c C-i C-p"])))
'(("Directive"
["translate_on" vhdl-template-directive-translate-on t]
@@ -3417,6 +3510,7 @@ STRING are replaced by `-' and substrings are converted to lower case."
["Buffer" vhdl-beautify-buffer t])
("Fix"
["Generic/Port Clause" vhdl-fix-clause t]
+ ["Generic/Port Clause Buffer" vhdl-fix-clause t]
"--"
["Case Region" vhdl-fix-case-region (mark)]
["Case Buffer" vhdl-fix-case-buffer t]
@@ -3449,11 +3543,13 @@ STRING are replaced by `-' and substrings are converted to lower case."
("Mode"
["Electric Mode"
(progn (customize-set-variable 'vhdl-electric-mode
- (not vhdl-electric-mode)))
+ (not vhdl-electric-mode))
+ (vhdl-mode-line-update))
:style toggle :selected vhdl-electric-mode :keys "C-c C-m C-e"]
["Stutter Mode"
(progn (customize-set-variable 'vhdl-stutter-mode
- (not vhdl-stutter-mode)))
+ (not vhdl-stutter-mode))
+ (vhdl-mode-line-update))
:style toggle :selected vhdl-stutter-mode :keys "C-c C-m C-s"]
["Indent Tabs Mode"
(progn (customize-set-variable 'vhdl-indent-tabs-mode
@@ -3515,6 +3611,8 @@ STRING are replaced by `-' and substrings are converted to lower case."
(customize-set-variable 'vhdl-compile-use-local-error-regexp
(not vhdl-compile-use-local-error-regexp))
:style toggle :selected vhdl-compile-use-local-error-regexp]
+ ["Makefile Default Targets..."
+ (customize-option 'vhdl-makefile-default-targets) t]
["Makefile Generation Hook..."
(customize-option 'vhdl-makefile-generation-hook) t]
["Default Library Name" (customize-option 'vhdl-default-library) t]
@@ -3527,7 +3625,7 @@ STRING are replaced by `-' and substrings are converted to lower case."
(list '87 (cadr vhdl-standard)))
(vhdl-activate-customizations))
:style radio :selected (eq '87 (car vhdl-standard))]
- ["VHDL'93"
+ ["VHDL'93/02"
(progn (customize-set-variable 'vhdl-standard
(list '93 (cadr vhdl-standard)))
(vhdl-activate-customizations))
@@ -3580,6 +3678,10 @@ STRING are replaced by `-' and substrings are converted to lower case."
["Always"
(customize-set-variable 'vhdl-use-direct-instantiation 'always)
:style radio :selected (eq 'always vhdl-use-direct-instantiation)])
+ ["Include Array Index and Record Field in Sensitivity List"
+ (customize-set-variable 'vhdl-array-index-record-field-in-sensitivity-list
+ (not vhdl-array-index-record-field-in-sensitivity-list))
+ :style toggle :selected vhdl-array-index-record-field-in-sensitivity-list]
"--"
["Customize Group..." (customize-group 'vhdl-style) t])
("Naming"
@@ -3676,7 +3778,10 @@ STRING are replaced by `-' and substrings are converted to lower case."
:style radio :selected (eq 'sync vhdl-reset-kind)]
["Asynchronous"
(customize-set-variable 'vhdl-reset-kind 'async)
- :style radio :selected (eq 'async vhdl-reset-kind)])
+ :style radio :selected (eq 'async vhdl-reset-kind)]
+ ["Query"
+ (customize-set-variable 'vhdl-reset-kind 'query)
+ :style radio :selected (eq 'query vhdl-reset-kind)])
["Reset is Active High"
(customize-set-variable 'vhdl-reset-active-high
(not vhdl-reset-active-high))
@@ -3966,6 +4071,10 @@ STRING are replaced by `-' and substrings are converted to lower case."
(customize-set-variable 'vhdl-indent-syntax-based
(not vhdl-indent-syntax-based))
:style toggle :selected vhdl-indent-syntax-based]
+ ["Indent Comments Like Next Code Line"
+ (customize-set-variable 'vhdl-indent-comment-like-next-code-line
+ (not vhdl-indent-comment-like-next-code-line))
+ :style toggle :selected vhdl-indent-comment-like-next-code-line]
["Word Completion is Case Sensitive"
(customize-set-variable 'vhdl-word-completion-case-sensitive
(not vhdl-word-completion-case-sensitive))
@@ -4009,7 +4118,7 @@ STRING are replaced by `-' and substrings are converted to lower case."
"^\\s-*\\(\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\s-+\\(\"?\\(\\w\\|\\s_\\)+\"?\\)"
4)
("Instance"
- "^\\s-*\\(\\(\\w\\|\\s_\\)+\\s-*:\\(\\s-\\|\n\\)*\\(\\w\\|\\s_\\)+\\)\\(\\s-\\|\n\\)+\\(generic\\|port\\)\\s-+map\\>"
+ "^\\s-*\\(\\(\\w\\|\\s_\\)+\\s-*:\\(\\s-\\|\n\\)*\\(entity\\s-+\\(\\w\\|\\s_\\)+\\.\\)?\\(\\w\\|\\s_\\)+\\)\\(\\s-\\|\n\\)+\\(generic\\|port\\)\\s-+map\\>"
1)
("Component"
"^\\s-*\\(component\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)"
@@ -4193,8 +4302,10 @@ Usage:
with a comment in between.
`--CR' comments out code on that line. Re-hitting CR comments
out following lines.
- `C-c c' comments out a region if not commented out,
- uncomments a region if already commented out.
+ `C-c C-c' comments out a region if not commented out,
+ uncomments a region if already commented out. Option
+ `comment-style' defines where the comment characters
+ should be placed (beginning of line, indent, etc.).
You are prompted for comments after object definitions (i.e. signals,
variables, constants, ports) and after subprogram and process
@@ -4215,7 +4326,8 @@ Usage:
`TAB' indents a line if at the beginning of the line. The amount of
indentation is specified by option `vhdl-basic-offset'. `C-c C-i C-l'
always indents the current line (is bound to `TAB' if option
- `vhdl-intelligent-tab' is nil).
+ `vhdl-intelligent-tab' is nil). If a region is active, `TAB' indents
+ the entire region.
Indentation can be done for a group of lines (`C-c C-i C-g'), a region
\(`M-C-\\') or the entire buffer (menu). Argument and port lists are
@@ -4229,6 +4341,10 @@ Usage:
Syntax-based indentation can be very slow in large files. Option
`vhdl-indent-syntax-based' allows to use faster but simpler indentation.
+ Option `vhdl-indent-comment-like-next-code-line' controls whether
+ comment lines are indented like the preceding or like the following code
+ line.
+
ALIGNMENT:
The alignment functions align operators, keywords, and inline comments
@@ -4357,12 +4473,12 @@ Usage:
STRUCTURAL COMPOSITION:
- Enables simple structural composition. `C-c C-c C-n' creates a skeleton
+ Enables simple structural composition. `C-c C-m C-n' creates a skeleton
for a new component. Subcomponents (i.e. component declaration and
instantiation) can be automatically placed from a previously read port
- \(`C-c C-c C-p') or directly from the hierarchy browser (`P'). Finally,
+ \(`C-c C-m C-p') or directly from the hierarchy browser (`P'). Finally,
all subcomponents can be automatically connected using internal signals
- and ports (`C-c C-c C-w') following these rules:
+ and ports (`C-c C-m C-w') following these rules:
- subcomponent actual ports with same name are considered to be
connected by a signal (internal signal or port)
- signals that are only inputs to subcomponents are considered as
@@ -4383,25 +4499,25 @@ Usage:
Component declarations can be placed in a components package (option
`vhdl-use-components-package') which can be automatically generated for
- an entire directory or project (`C-c C-c M-p'). The VHDL'93 direct
+ an entire directory or project (`C-c C-m M-p'). The VHDL'93 direct
component instantiation is also supported (option
`vhdl-use-direct-instantiation').
-| Configuration declarations can automatically be generated either from
-| the menu (`C-c C-c C-f') (for the architecture the cursor is in) or from
-| the speedbar menu (for the architecture under the cursor). The
-| configurations can optionally be hierarchical (i.e. include all
-| component levels of a hierarchical design, option
-| `vhdl-compose-configuration-hierarchical') or include subconfigurations
-| (option `vhdl-compose-configuration-use-subconfiguration'). For
-| subcomponents in hierarchical configurations, the most-recently-analyzed
-| (mra) architecture is selected. If another architecture is desired, it
-| can be marked as most-recently-analyzed (speedbar menu) before
-| generating the configuration.
-|
-| Note: Configurations of subcomponents (i.e. hierarchical configuration
-| declarations) are currently not considered when displaying
-| configurations in speedbar.
+ Configuration declarations can automatically be generated either from
+ the menu (`C-c C-m C-f') (for the architecture the cursor is in) or from
+ the speedbar menu (for the architecture under the cursor). The
+ configurations can optionally be hierarchical (i.e. include all
+ component levels of a hierarchical design, option
+ `vhdl-compose-configuration-hierarchical') or include subconfigurations
+ (option `vhdl-compose-configuration-use-subconfiguration'). For
+ subcomponents in hierarchical configurations, the most-recently-analyzed
+ (mra) architecture is selected. If another architecture is desired, it
+ can be marked as most-recently-analyzed (speedbar menu) before
+ generating the configuration.
+
+ Note: Configurations of subcomponents (i.e. hierarchical configuration
+ declarations) are currently not considered when displaying
+ configurations in speedbar.
See the options group `vhdl-compose' for all relevant user options.
@@ -4433,11 +4549,13 @@ Usage:
The Makefile's default target \"all\" compiles the entire design, the
target \"clean\" removes it and the target \"library\" creates the
- library directory if not existent. The Makefile also includes a target
- for each primary library unit which allows selective compilation of this
- unit, its secondary units and its subhierarchy (example: compilation of
- a design specified by a configuration). User specific parts can be
- inserted into a Makefile with option `vhdl-makefile-generation-hook'.
+ library directory if not existent. These target names can be customized
+ by option `vhdl-makefile-default-targets'. The Makefile also includes a
+ target for each primary library unit which allows selective compilation
+ of this unit, its secondary units and its subhierarchy (example:
+ compilation of a design specified by a configuration). User specific
+ parts can be inserted into a Makefile with option
+ `vhdl-makefile-generation-hook'.
Limitations:
- Only library units and dependencies within the current library are
@@ -4483,7 +4601,7 @@ Usage:
VHDL STANDARDS:
The VHDL standards to be used are specified in option `vhdl-standard'.
- Available standards are: VHDL'87/'93, VHDL-AMS, and Math Packages.
+ Available standards are: VHDL'87/'93(02), VHDL-AMS, and Math Packages.
KEYWORD CASE:
@@ -4559,6 +4677,9 @@ Usage:
- Out parameters of procedures are considered to be read.
Use option `vhdl-entity-file-name' to specify the entity file name
\(used to obtain the port names).
+ Use option `vhdl-array-index-record-field-in-sensitivity-list' to
+ specify whether to include array indices and record fields in
+ sensitivity lists.
CODE FIXING:
@@ -4632,16 +4753,17 @@ releases. You are kindly invited to participate in beta testing. Subscribe
to above mailing lists by sending an email to .
VHDL Mode is officially distributed at
-URL `http://opensource.ethz.ch/emacs/vhdl-mode.html'
+http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
where the latest version can be found.
Known problems:
---------------
-- Indentation bug in simultaneous if- and case-statements (VHDL-AMS).
- XEmacs: Incorrect start-up when automatically opening speedbar.
- XEmacs: Indentation in XEmacs 21.4 (and higher).
+- Indentation incorrect for new 'postponed' VHDL keyword.
+- Indentation incorrect for 'protected body' construct.
The VHDL Mode Authors
@@ -4764,7 +4886,7 @@ Key bindings:
;;; Keywords and standardized words
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(defconst vhdl-93-keywords
+(defconst vhdl-02-keywords
'(
"abs" "access" "after" "alias" "all" "and" "architecture" "array"
"assert" "attribute"
@@ -4779,7 +4901,7 @@ Key bindings:
"map" "mod"
"nand" "new" "next" "nor" "not" "null"
"of" "on" "open" "or" "others" "out"
- "package" "port" "postponed" "procedure" "process" "pure"
+ "package" "port" "postponed" "procedure" "process" "protected" "pure"
"range" "record" "register" "reject" "rem" "report" "return"
"rol" "ror"
"select" "severity" "shared" "signal" "sla" "sll" "sra" "srl" "subtype"
@@ -4789,7 +4911,7 @@ Key bindings:
"wait" "when" "while" "with"
"xnor" "xor"
)
- "List of VHDL'93 keywords.")
+ "List of VHDL'02 keywords.")
(defconst vhdl-ams-keywords
'(
@@ -4822,7 +4944,7 @@ Key bindings:
)
"List of Verilog keywords as candidate for additional reserved words.")
-(defconst vhdl-93-types
+(defconst vhdl-02-types
'(
"boolean" "bit" "bit_vector" "character" "severity_level" "integer"
"real" "time" "natural" "positive" "string" "line" "text" "side"
@@ -4830,25 +4952,72 @@ Key bindings:
"std_logic" "std_logic_vector"
"std_ulogic" "std_ulogic_vector"
)
- "List of VHDL'93 standardized types.")
+ "List of VHDL'02 standardized types.")
(defconst vhdl-ams-types
+ ;; standards: IEEE Std 1076.1-2007, IEEE Std 1076.1.1-2004
'(
+ ;; package `standard'
"domain_type" "real_vector"
- ;; from `nature_pkg' package
- "voltage" "current" "electrical" "position" "velocity" "force"
- "mechanical_vf" "mechanical_pf" "rotvel" "torque" "rotational"
- "pressure" "flowrate" "fluid"
- )
+ ;; package `energy_systems'
+ "energy" "power" "periodicity" "real_across" "real_through" "unspecified"
+ "unspecified_vector" "energy_vector" "power_vector" "periodicity_vector"
+ "real_across_vector" "real_through_vector"
+ ;; package `electrical_systems'
+ "voltage" "current" "charge" "resistance" "conductance" "capacitance"
+ "mmf" "electric_flux" "electric_flux_density" "electric_field_strength"
+ "magnetic_flux" "magnetic_flux_density" "magnetic_field_strength"
+ "inductance" "reluctance" "electrical" "electrical_vector" "magnetic"
+ "magnetic_vector" "voltage_vector" "current_vector" "mmf_vector"
+ "magnetic_flux_vector" "charge_vector" "resistance_vector"
+ "conductance_vector" "capacitance_vector" "electric_flux_vector"
+ "electric_flux_density_vector" "electric_field_strength_vector"
+ "magnetic_flux_density_vector" "magnetic_field_strength_vector"
+ "inductance_vector" "reluctance_vector" "ground"
+ ;; package `mechanical_systems'
+ "displacement" "force" "velocity" "acceleration" "mass" "stiffness"
+ "damping" "momentum" "angle" "torque" "angular_velocity"
+ "angular_acceleration" "moment_inertia" "angular_momentum"
+ "angular_stiffness" "angular_damping" "translational"
+ "translational_vector" "translational_velocity"
+ "translational_velocity_vector" "rotational" "rotational_vector"
+ "rotational_velocity" "rotational_velocity_vector" "displacement_vector"
+ "force_vector" "velocity_vector" "force_velocity_vector" "angle_vector"
+ "torque_vector" "angular_velocity_vector" "torque_velocity_vector"
+ "acceleration_vector" "mass_vector" "stiffness_vector" "damping_vector"
+ "momentum_vector" "angular_acceleration_vector" "moment_inertia_vector"
+ "angular_momentum_vector" "angular_stiffness_vector"
+ "angular_damping_vector" "anchor" "translational_v_ref"
+ "rotational_v_ref" "translational_v" "rotational_v"
+ ;; package `radiant_systems'
+ "illuminance" "luminous_flux" "luminous_intensity" "irradiance" "radiant"
+ "radiant_vector" "luminous_intensity_vector" "luminous_flux_vector"
+ "illuminance_vector" "irradiance_vector"
+ ;; package `thermal_systems'
+ "temperature" "heat_flow" "thermal_capacitance" "thermal_resistance"
+ "thermal_conductance" "thermal" "thermal_vector" "temperature_vector"
+ "heat_flow_vector" "thermal_capacitance_vector"
+ "thermal_resistance_vector" "thermal_conductance_vector"
+ ;; package `fluidic_systems'
+ "pressure" "vflow_rate" "mass_flow_rate" "volume" "density" "viscosity"
+ "fresistance" "fconductance" "fcapacitance" "inertance" "cfresistance"
+ "cfcapacitance" "cfinertance" "cfconductance" "fluidic" "fluidic_vector"
+ "compressible_fluidic" "compressible_fluidic_vector" "pressure_vector"
+ "vflow_rate_vector" "mass_flow_rate_vector" "volume_vector"
+ "density_vector" "viscosity_vector" "fresistance_vector"
+ "fconductance_vector" "fcapacitance_vector" "inertance_vector"
+ "cfresistance_vector" "cfconductance_vector" "cfcapacitance_vector"
+ "cfinertance_vector"
+ )
"List of VHDL-AMS standardized types.")
(defconst vhdl-math-types
'(
- "complex" "complex_polar"
+ "complex" "complex_polar" "positive_real" "principal_value"
)
"List of Math Packages standardized types.")
-(defconst vhdl-93-attributes
+(defconst vhdl-02-attributes
'(
"base" "left" "right" "high" "low" "pos" "val" "succ"
"pred" "leftof" "rightof" "range" "reverse_range"
@@ -4858,7 +5027,7 @@ Key bindings:
"simple_name" "instance_name" "path_name"
"foreign"
)
- "List of VHDL'93 standardized attributes.")
+ "List of VHDL'02 standardized attributes.")
(defconst vhdl-ams-attributes
'(
@@ -4869,7 +5038,7 @@ Key bindings:
)
"List of VHDL-AMS standardized attributes.")
-(defconst vhdl-93-enum-values
+(defconst vhdl-02-enum-values
'(
"true" "false"
"note" "warning" "error" "failure"
@@ -4878,7 +5047,7 @@ Key bindings:
"fs" "ps" "ns" "us" "ms" "sec" "min" "hr"
"right" "left"
)
- "List of VHDL'93 standardized enumeration values.")
+ "List of VHDL'02 standardized enumeration values.")
(defconst vhdl-ams-enum-values
'(
@@ -4888,22 +5057,38 @@ Key bindings:
)
"List of VHDL-AMS standardized enumeration values.")
+(defconst vhdl-ams-constants
+ ;; standard: IEEE Std 1076.1.1-2004
+ '(
+ ;; package `fundamental_constants'
+ "phys_q" "phys_eps0" "phys_mu0" "phys_k" "phys_gravity" "phys_ctok"
+ "phys_c" "phys_h" "phys_h_over_2_pi" "yocto" "zepto" "atto" "femto"
+ "pico" "nano" "micro" "milli" "centi" "deci" "deka" "hecto" "kilo" "mega"
+ "giga" "tera" "peta" "exa" "zetta" "yotta" "deca"
+ ;; package `material_constants'
+ "phys_eps_si" "phys_eps_sio2" "phys_e_si" "phys_e_sio2" "phys_e_poly"
+ "phys_nu_si" "phys_nu_poly" "phys_rho_poly" "phys_rho_sio2"
+ "ambient_temperature" "ambient_pressure" "ambient_illuminance"
+ )
+ "List of VHDL-AMS standardized constants.")
+
(defconst vhdl-math-constants
+ ;; standard: IEEE Std 1076.2-1996
'(
- "math_e" "math_1_over_e"
- "math_pi" "math_two_pi" "math_1_over_pi"
- "math_half_pi" "math_q_pi" "math_3_half_pi"
- "math_log_of_2" "math_log_of_10" "math_log2_of_e" "math_log10_of_e"
- "math_sqrt2" "math_sqrt1_2" "math_sqrt_pi"
- "math_deg_to_rad" "math_rad_to_deg"
- "cbase_1" "cbase_j" "czero"
+ "math_1_over_e" "math_1_over_pi" "math_1_over_sqrt_2" "math_2_pi"
+ "math_3_pi_over_2" "math_cbase_1" "math_cbase_j" "math_czero"
+ "math_deg_to_rad" "math_e" "math_log10_of_e" "math_log2_of_e"
+ "math_log_of_10" "math_log_of_2" "math_pi" "math_pi_over_2"
+ "math_pi_over_3" "math_pi_over_4" "math_rad_to_deg" "math_sqrt_2"
+ "math_sqrt_pi"
)
"List of Math Packages standardized constants.")
-(defconst vhdl-93-functions
+(defconst vhdl-02-functions
'(
"now" "resolved" "rising_edge" "falling_edge"
- "read" "readline" "write" "writeline" "endfile"
+ "read" "readline" "hread" "oread" "write" "writeline" "hwrite" "owrite"
+ "endfile"
"resize" "is_X" "std_match"
"shift_left" "shift_right" "rotate_left" "rotate_right"
"to_unsigned" "to_signed" "to_integer"
@@ -4913,25 +5098,27 @@ Key bindings:
"shl" "shr" "ext" "sxt"
"deallocate"
)
- "List of VHDL'93 standardized functions.")
+ "List of VHDL'02 standardized functions.")
(defconst vhdl-ams-functions
'(
+ ;; package `standard'
"frequency"
)
"List of VHDL-AMS standardized functions.")
(defconst vhdl-math-functions
+ ;; standard: IEEE Std 1076.2-1996
'(
- "sign" "ceil" "floor" "round" "trunc" "fmax" "fmin" "uniform"
- "sqrt" "cbrt" "exp" "log"
- "sin" "cos" "tan" "arcsin" "arccos" "arctan"
- "sinh" "cosh" "tanh" "arcsinh" "arccosh" "arctanh"
- "cmplx" "complex_to_polar" "polar_to_complex" "arg" "conj"
+ "arccos" "arccosh" "arcsin" "arcsinh" "arctan" "arctanh" "arg"
+ "cbrt" "ceil" "cmplx" "complex_to_polar" "conj" "cos" "cosh" "exp"
+ "floor" "get_principal_value" "log" "log10" "log2" "polar_to_complex"
+ "realmax" "realmin" "round" "sign" "sin" "sinh" "sqrt"
+ "tan" "tanh" "trunc" "uniform"
)
"List of Math Packages standardized functions.")
-(defconst vhdl-93-packages
+(defconst vhdl-02-packages
'(
"std_logic_1164" "numeric_std" "numeric_bit"
"standard" "textio"
@@ -4939,12 +5126,13 @@ Key bindings:
"std_logic_misc" "std_logic_textio"
"ieee" "std" "work"
)
- "List of VHDL'93 standardized packages and libraries.")
+ "List of VHDL'02 standardized packages and libraries.")
(defconst vhdl-ams-packages
'(
- ;; from `nature_pkg' package
- "nature_pkg"
+ "fundamental_constants" "material_constants" "energy_systems"
+ "electrical_systems" "mechanical_systems" "radiant_systems"
+ "thermal_systems" "fluidic_systems"
)
"List of VHDL-AMS standardized packages and libraries.")
@@ -4990,6 +5178,9 @@ Key bindings:
(defvar vhdl-enum-values-regexp nil
"Regexp for VHDL standardized enumeration values.")
+(defvar vhdl-constants-regexp nil
+ "Regexp for VHDL standardized constants.")
+
(defvar vhdl-functions-regexp nil
"Regexp for VHDL standardized functions.")
@@ -5002,29 +5193,50 @@ Key bindings:
(defvar vhdl-directive-keywords-regexp nil
"Regexp for compiler directive keywords.")
+(defun vhdl-upcase-list (condition list)
+ "Upcase all elements in LIST based on CONDITION."
+ (when condition
+ (let ((tmp-list list))
+ (while tmp-list
+ (setcar tmp-list (upcase (car tmp-list)))
+ (setq tmp-list (cdr tmp-list)))))
+ list)
+
(defun vhdl-words-init ()
"Initialize reserved words."
(setq vhdl-keywords
- (append vhdl-93-keywords
- (when (vhdl-standard-p 'ams) vhdl-ams-keywords)))
+ (vhdl-upcase-list
+ (and vhdl-highlight-case-sensitive vhdl-upper-case-keywords)
+ (append vhdl-02-keywords
+ (when (vhdl-standard-p 'ams) vhdl-ams-keywords))))
(setq vhdl-types
- (append vhdl-93-types
- (when (vhdl-standard-p 'ams) vhdl-ams-types)
- (when (vhdl-standard-p 'math) vhdl-math-types)))
+ (vhdl-upcase-list
+ (and vhdl-highlight-case-sensitive vhdl-upper-case-types)
+ (append vhdl-02-types
+ (when (vhdl-standard-p 'ams) vhdl-ams-types)
+ (when (vhdl-standard-p 'math) vhdl-math-types))))
(setq vhdl-attributes
- (append vhdl-93-attributes
- (when (vhdl-standard-p 'ams) vhdl-ams-attributes)))
+ (vhdl-upcase-list
+ (and vhdl-highlight-case-sensitive vhdl-upper-case-attributes)
+ (append vhdl-02-attributes
+ (when (vhdl-standard-p 'ams) vhdl-ams-attributes))))
(setq vhdl-enum-values
- (append vhdl-93-enum-values
- (when (vhdl-standard-p 'ams) vhdl-ams-enum-values)))
+ (vhdl-upcase-list
+ (and vhdl-highlight-case-sensitive vhdl-upper-case-enum-values)
+ (append vhdl-02-enum-values
+ (when (vhdl-standard-p 'ams) vhdl-ams-enum-values))))
(setq vhdl-constants
- (append (when (vhdl-standard-p 'math) vhdl-math-constants)))
+ (vhdl-upcase-list
+ (and vhdl-highlight-case-sensitive vhdl-upper-case-constants)
+ (append (when (vhdl-standard-p 'ams) vhdl-ams-constants)
+ (when (vhdl-standard-p 'math) vhdl-math-constants)
+ '(""))))
(setq vhdl-functions
- (append vhdl-93-functions
+ (append vhdl-02-functions
(when (vhdl-standard-p 'ams) vhdl-ams-functions)
(when (vhdl-standard-p 'math) vhdl-math-functions)))
(setq vhdl-packages
- (append vhdl-93-packages
+ (append vhdl-02-packages
(when (vhdl-standard-p 'ams) vhdl-ams-packages)
(when (vhdl-standard-p 'math) vhdl-math-packages)))
(setq vhdl-reserved-words
@@ -5039,6 +5251,8 @@ Key bindings:
(concat "\\<\\(" (regexp-opt vhdl-attributes) "\\)\\>"))
(setq vhdl-enum-values-regexp
(concat "\\<\\(" (regexp-opt vhdl-enum-values) "\\)\\>"))
+ (setq vhdl-constants-regexp
+ (concat "\\<\\(" (regexp-opt vhdl-constants) "\\)\\>"))
(setq vhdl-functions-regexp
(concat "\\<\\(" (regexp-opt vhdl-functions) "\\)\\>"))
(setq vhdl-packages-regexp
@@ -5090,7 +5304,7 @@ We cannot use just `word' syntax class since `_' cannot be in word
class. Putting underscore in word class breaks forward word movement
behavior that users are familiar with.")
-(defconst vhdl-case-header-key "case[( \t\n][^;=>]+[) \t\n]is"
+(defconst vhdl-case-header-key "case[( \t\n\r\f][^;=>]+[) \t\n\r\f]is"
"Regexp describing a case statement header key.")
(defconst vhdl-label-key
@@ -5318,6 +5532,17 @@ the offset is simply returned."
"Check if point is in a string."
(eq (vhdl-in-literal) 'string))
+(defun vhdl-in-quote-p ()
+ "Check if point is in a quote ('x')."
+ (or (and (> (point) (point-min))
+ (< (1+ (point)) (point-max))
+ (= (char-before (point)) ?\')
+ (= (char-after (1+ (point))) ?\'))
+ (and (> (1- (point)) (point-min))
+ (< (point) (point-max))
+ (= (char-before (1- (point))) ?\')
+ (= (char-after (point)) ?\'))))
+
(defun vhdl-in-literal ()
"Determine if point is in a VHDL literal."
(save-excursion
@@ -5328,6 +5553,12 @@ the offset is simply returned."
((vhdl-beginning-of-macro) 'pound)
(t nil)))))
+(defun vhdl-in-extended-identifier-p ()
+ "Determine if point is inside extended identifier (delimited by '\')."
+ (save-match-data
+ (and (save-excursion (re-search-backward "\\\\" (vhdl-point 'bol) t))
+ (save-excursion (re-search-forward "\\\\" (vhdl-point 'eol) t)))))
+
(defun vhdl-forward-comment (&optional direction)
"Skip all comments (including whitespace). Skip backwards if DIRECTION is
negative, skip forward otherwise."
@@ -5335,20 +5566,30 @@ negative, skip forward otherwise."
(if (and direction (< direction 0))
;; skip backwards
(progn
- (skip-chars-backward " \t\n")
+ (skip-chars-backward " \t\n\r\f")
(while (re-search-backward "^[^\"-]*\\(\\(-?\"[^\"]*\"\\|-[^\"-]\\)[^\"-]*\\)*\\(--\\)" (vhdl-point 'bol) t)
(goto-char (match-beginning 3))
- (skip-chars-backward " \t\n")))
+ (skip-chars-backward " \t\n\r\f")))
;; skip forwards
- (skip-chars-forward " \t\n")
+ (skip-chars-forward " \t\n\r\f")
(while (looking-at "--.*")
(goto-char (match-end 0))
- (skip-chars-forward " \t\n"))))
+ (skip-chars-forward " \t\n\r\f"))))
;; XEmacs hack: work around buggy `forward-comment' in XEmacs 21.4+
(unless (and (featurep 'xemacs) (string< "21.2" emacs-version))
(defalias 'vhdl-forward-comment 'forward-comment))
+(defun vhdl-back-to-indentation ()
+ "Move point to the first non-whitespace character on this line."
+ (interactive)
+ (beginning-of-line 1)
+ (skip-syntax-forward " " (vhdl-point 'eol)))
+
+;; XEmacs hack: work around old `back-to-indentation' in XEmacs
+(when (featurep 'xemacs)
+ (defalias 'back-to-indentation 'vhdl-back-to-indentation))
+
;; This is the best we can do in Win-Emacs.
(defun vhdl-win-il (&optional lim)
"Determine if point is in a VHDL literal."
@@ -5513,7 +5754,7 @@ that point, else nil."
(and
(save-excursion
(forward-sexp)
- (skip-chars-forward " \t\n")
+ (skip-chars-forward " \t\n\r\f")
(not (looking-at "is\\b[^_]")))
(save-excursion
(backward-sexp)
@@ -5553,12 +5794,12 @@ corresponding \"begin\" keyword, else return nil."
"is"))))
(defconst vhdl-begin-fwd-re
- "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\|units\\|record\\|for\\)\\b\\([^_]\\|\\'\\)"
+ "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\(\\s-+body\\)?\\|units\\|use\\|record\\|protected\\(\\s-+body\\)?\\|for\\)\\b\\([^_]\\|\\'\\)"
"A regular expression for searching forward that matches all known
\"begin\" keywords.")
(defconst vhdl-begin-bwd-re
- "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\|units\\|record\\|for\\)\\b[^_]"
+ "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\(\\s-+body\\)?\\|units\\|use\\|record\\|protected\\(\\s-+body\\)?\\|for\\)\\b[^_]"
"A regular expression for searching backward that matches all known
\"begin\" keywords.")
@@ -5591,21 +5832,21 @@ keyword."
(and (/= (following-char) ?\;)
(not (looking-at "is\\|begin\\|process\\|procedural\\|block")))))
t)
- ;; "begin", "then":
- ((looking-at "be\\|t")
+ ;; "begin", "then", "use":
+ ((looking-at "be\\|t\\|use")
t)
;; "else":
((and (looking-at "e")
;; make sure that the "else" isn't inside a
;; conditional signal assignment.
(save-excursion
- (re-search-backward ";\\|\\bwhen\\b[^_]" lim 'move)
+ (vhdl-re-search-backward ";\\|\\bwhen\\b[^_]" lim 'move)
(or (eq (following-char) ?\;)
(eq (point) lim))))
t)
;; "block", "generate", "loop", "process", "procedural",
- ;; "units", "record":
- ((and (looking-at "bl\\|[glpur]")
+ ;; "units", "record", "protected body":
+ ((and (looking-at "block\\|generate\\|loop\\|process\\|procedural\\|protected\\(\\s-+body\\)?\\|units\\|record")
(save-excursion
(backward-sexp)
(not (looking-at "end\\s-+\\w"))))
@@ -5633,7 +5874,7 @@ keyword."
(cond
((looking-at "is\\|block\\|generate\\|process\\|procedural")
"begin")
- ((looking-at "then")
+ ((looking-at "then\\|use")
"")
(t
"end")))
@@ -5648,6 +5889,9 @@ Assumes that the caller will make sure that we are not in the middle
of an identifier that just happens to contain a \"begin\" keyword."
(save-excursion
(and (looking-at vhdl-begin-fwd-re)
+ (or (not (looking-at "\\