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Re: [Gnucap-devel] Verilog - was: Re: Use of M as suffix for Mega

From: jbdavid
Subject: Re: [Gnucap-devel] Verilog - was: Re: Use of M as suffix for Mega
Date: Thu, 24 Aug 2006 17:11:18 -0700 (PDT)

1. I'd strongly suggest perl or python as scripting languages for netlist
a friend of mine had once done a spice-spectre-Verilog-AMS netlist
translator that
used an internal XML table and XSLT transformations.. 
everything in to XML database, then out to whichever format you wanted.. 
I can ask him if he'd be willing to contribute that.

2. What is different about the cadence AMSDesigner is that the digital and
analog are VERY closely integrated..  you can use both digital and analog
constructs in the same module..
Pretty sweet.. I'd like the same capability in a free tool, so I'm willing
to help work on it..
In fact after working with spectre (which at least had case sensitivity) 
I really want a simulator with Verilog syntax as the primary netlisting
IE a Joint icarus/gnucap build..
(but the XML idea keeps sticking in the back of my head too..)
just tell me where the subversion code repository is and how to check out
the code.. 

Jonathan, not a cad guy, not a software guy either. David

al davis-5 wrote:
> On Friday 18 August 2006 18:29, Svenn Are Bjerkem wrote:
> I am considering using a translator to support Spice syntax.  
> One big advantage of the translator approach is that several 
> translators can be made, for exact translation of several 
> variants.  I think most of these translators could be simple 
> awk programs.  With a few to start with, some others like 
> Spectre, Saber, and Touchstone could follow.
>> Most simulators that I use do not have both analog and
>> digital abilities but rely on probes to transport data from
>> the analog simulator to the digital simulator and back again.
>> If gnucap will handle both in one executable (like not
>> relying on icarus verilog for the digital part) I would say
>> it make no sense any longer to support spice syntax. You burn
>> some bridges, but then you can focus on keeping up to date
>> with the standard.
> What the others are missing is that by adding digital capability 
> to the analog engine, fully integrated, digital techniques can 
> be applied to the analog portion, or even to pure analog 
> circuits.  Gnucap already does some of this.
>> Look at what Synopsys is doing to HSPICE: They cram it
>> together with their VCS digital simulator and call it
>> Discovery AMS. Cadence cram Spectre with their ncsim digital
>> simulators to get Spectre-AMS and Mentor Graphics cram eldo
>> with modelsim to get the ADMS.
> I have never used those programs.  I have not had access to 
> them.  I think I understand the underlying technology, but I 
> don't know anything about the user experience.  Can you give us 
> some info?
>> Will gnucap be able to replace all that? I must be missing
>> something here.
> Eventually, if I can get funding or help.  It is not as hard as 
> they make it out to be, but does take time.  Gnucap is not 
> Spice.  It does not have a lot of the baggage that makes Spice 
> so big and hard to work on.  It does have a real mixed-mode 
> engine that isn't being fully utilized.
>> Future is Verilog-AMS or VHDL-AMS give or take what continent
>> you live on. I prefer Verilog-AMS just because I hate writing
>> all those port descriptions in VHDL.
> There is also a difference in discipline.  I don't know any 
> analog designers who like VHDL, but I know several who think 
> Verilog is the best possible.  Digital designers seem to lean 
> more to VHDL.
> There is also a difference in accessability of the standard 
> document.  The Verilog-AMS LRM can be downloaded from 
> accellera's web site, with no hassles.  The VHDL-AMS LRM is 
> handled by IEEE, and they want money for it.
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