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Re: [Gnucap-devel] Problem with logic elements on transient simulation

From: al davis
Subject: Re: [Gnucap-devel] Problem with logic elements on transient simulation
Date: Thu, 15 Nov 2012 16:52:42 -0500
User-agent: KMail/1.13.5 (Linux/2.6.32-5-amd64; KDE/4.4.5; x86_64; ; )

On Monday 05 November 2012, Rupert Swarbrick wrote:
> (1) Is this a bug? (I presume so, but thought I should
> check!)

I now have a proper fix for the bug.

It's really pretty simple ..

In .. line 76.


That's all .. it works correctly now.

> (2) Has anyone written down an explanation of how d_logic
> should work somewhere? I'd happily search for a fix, but it
> feels like I'm stumbling around in the dark a little bit.

My Ph.D. dissertation.

It has been several years since anyone has worked on this code.  
I had been putting it off because it has been planned for a 
reorganization as part of Verilog-AMS support.  It took a long 
time to notice the bug because not many people use the logic and 
mixed modes, which are not compatible with anything else.  The 
code is significant historically because it is the first 
published implementation of what later became the 
"connectmodule" concept.

Here is more of an explanation:

It looks like the bug was introduced with a code change from C 
to C++, particularly the LOGIC_NODE constructor.

The logic value of an analog node is set in 
LOGIC_NODE::to_logic, which is called by DEV_LOGIC::tr_accept 
(which will become part of a base class for logic devices in 

Inside LOGIC_NODE::to_logic, there is a test:
   "if (is_analog() &&  d_iter() < a_iter()) {"
which really asks the question of "is this an analog node that 
had a recent change that might be interpreted as a digital state 

The problem is that initially, d_iter()==a_iter() the less-than 
test fails, and it never got initialized.  The solution was 
simply to make the initial value of d_iter() -1, so the 
condition is initially true, so the logic value gets 

It only showed on the ground node because for all other analog 
nodes, a_iter() was set to a positive number on the first 
iteration, leading to initialization of the logic value.

> (3) Is this going to be irrelevant if/when upcoming
> VHDL/Verilog work gets merged?


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