[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Gnucap-devel] workarounds for the lack of nodeset

From: Felix Salfelder
Subject: [Gnucap-devel] workarounds for the lack of nodeset
Date: Wed, 24 Jul 2019 17:38:14 +0200
User-agent: NeoMutt/20170113 (1.7.2)

On Wed, Jul 17, 2019 at 02:33:06PM +0200, someone wrote:
>  I am with some collegues investigating an application that could make use
> of GNUcap strong points, such as the unified event queue and timestepping
> control. However, it most certainly requires that the circuit starts with a
> DC that contains charged capacitors.

Gnucap is interactive. simulation commands are processed in a defined
order, and you can do things in between. For example, run one analysis,
change a parameter, and then run another. typically, when you run a
first transient command, it does a dc analysis first. subsequent
transient commands don't (unless enforced). similarly, you can start the
first transient from a previously computed dc operating point (use the
"uic" flag). you have probably figured this out.

how to get the charge into the capacitor?

>  I suppose one could use workarounds. I was guessing along the lines of:
> using DC voltage sources instead of nodesets, then run a transient with very
> long time timesteps, to save the final state as an IC, and then reuse that
> state with UIC in the "actual" transient analysis that follows.

note that dc analysis is much the same as "a very long transient
analysis", with the inputs fixed. the state is saved automatically, and
a subsequent analysis will normally pick it up (useful for ac...).

The approach involves voltage sources in parallel to caps. it can be a
viable way to set initial conditions if you put a resistor in between.
the value of a resistor could be changed after one simulation using the
alter command, or by changing a parameter. the second simulation could
be a "tran uic", not touching the charge. in contrast, when changing the
netlist (i.e. add/remove components), the circuit state is lost -- so
you need that extra component and an extra node.

some commercial simulator has a switch that is on and off in
one or multiple out of ac/dc/tran simulation modes. this switch has
nothing to do with the "switch" in the default plugins. the mode switch
behaviour can however be imitated with a spice macro and an indicator
function implemented here [1,2].

>  However, I would much rather have a proper nodeset support in DC/IC
> analysis. [..]

there is a nodeset command in an old and obsolete gnucap fork [3]. It
could be (decrufted and) modified to compile with the current version.
it remains to figure what 'proper' means.

simply setting the node values might not immediately work as expected.
nodeset was meant to aid convergence, and not for modelling. if there
are two nodes, with a (default) cap across, and one node is set to high
(e.g.  using nodeset), it will be back down after the first iteration of
the solver. must to actually "read in" the voltage across (and latch
a corresponding charge) in tr_begin, for nodeset to have an effect. not
sure if this is a good idea though. While modifying the cap, you will
find that you could as well set the initial charge directly. c.f.
verilog-ams "analog initial" block: it is part of the model, and not a
nodeset. you would likely set the initial charge (= state of the
component), but not a node voltage, in such a block.

some related hacks, such as a cap that pretends to be a voltage source
during a DC analysis, exist in gnucap-uf. fortunately, you can easily
replace capacitor models, with the "load" command. the same holds for
commands like "tran".



reply via email to

[Prev in Thread] Current Thread [Next in Thread]