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Re: modelgen & veriloga
Re: modelgen & veriloga
Tue, 25 Feb 2020 14:01:21 +0100
On Tue, Feb 25, 2020 at 12:51:46AM +0100, Vincent Pinon wrote:
> I have read on your site that ADMS seems sort of a dead-end to load
> VerilogA code, which I agree after struggling to get these models
> understood by the NGspice back-end (with no success)! I read you were
> thinking of evolving your modelgen tool for this kind of task,
> unfortunately the gnucap-modelgen-verilog repository on savannah is
Gnucap supports the adms ngspice backend basically 1:1 with all its
features and limitations. This is implemented as the "spice-wrapper",
and some fiddling is required to make it run. For models that don't
work, there is no point. Verilog-ADMS only contains a subset of
Verilog-A, and adds other things. Verilog-AMS is a superset of
Verilog-A, and gnucap has been designed with mixed signal in mind.
Some time ago, "gnucap-adms" started from the adms templates for spice
in an attempt to fix the limitations. When facing the dead-end, I
started to rearrange things, mainly inspired by gnucap-modelgen. Now,
the xml stuff needs replacement, and I was unsure if I should do
gnucap-modelgen-verilog or use some other Verilog-AMS tool. And no such
tool has emerged in the meantime.
The spice templates produce code that computes matrix stamps and current
contributions. These represent voltage controlled current sources, and
there is considerable overhead in the templates that relates to
simulator internals. In contrast, gnucap-modelgen translates a model
described in terms of voltage dependent conductances and currents into a
subcircuit component built from controlled sources. With this, modelgen
does not need to know about the matrix interface, nor about low-level
algorithmic details. Note that modelgen lacks the required automatic
gnucap-adms is still similar to the spice backend in many ways, and
demonstrates some issues there. however, it has moved to the "subcircuit
architecture". unlike the spice templates, it supports subcircuit
components including current controlled current sources, and controlled
voltage sources, and has operators such as ddt and idt. The controlled
sources are derived from "cpoly_g", which is used in modelgen
components. "ddx" is where I gave up -- it was not fun anymore, when
changes to adms internals were required.
> I am thinking of spending some time on this for the months to come (I
> already know analog simulation & C++ quite well) Do you have any
> pointer to help me to start? Code, discussions, advice, ideas...
This sounds amazing. What we really need to break the deadlock is
gnucap-modelgen-verilog. I suggest to implement it one step at a time
and reuse as much as possible. In a nutshell that is
- a simple verilog parser. like mg_in.cc (to grow as/where needed).
lex/yacc looks compelling, but it can be a can of worms.
- make a subcircuit with components in it, and deal with parameters.
relatively straightforward, but helps with understanding gnucap.
(carefully avoid MODEL_CARD)
- implement some Expression infrastructure (c.f. m_expression.h)
we need some derivatives and dependency tracking. partly nontrivial.
- eject components for @analog block. much like modelgen. perhaps use
or recycle the voltage and current sources from gnucap-adms.
- support dynamic expressions, ddt/idt/ddx
likely more nontrivial, but this is what you need for "verilog-A".
- (whatever I forgot)
- disciplines, logic blocks, connect modules, cross events
intersects with other work in progress. only a matter of time.
- make it run faster, in many ways.
Certainly a challenge. I am happy to discuss details. Please feel free
to ask. Al might have more to say about it.