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Re: possible nested modules bug

From: Felix Salfelder
Subject: Re: possible nested modules bug
Date: Thu, 25 Feb 2021 23:21:21 +0100

On Thu, Feb 25, 2021 at 04:26:59PM -0500, al davis wrote:
> The real bug is that nested modules are not supposed to work, as per
> the Verilog standard.  The correct behavior would be to flag the nested
> declaration as an error.

Ok, not sure how this is motivated, but fair enough. And much easier.

> The search has other problems, most significantly that it is slow,
> which is mostly caused by the linear search of everything.

CARD_LIST would have to carry some std::multimap. My last attempt
involved the ominous IString...

> In this case, the official "fix" should be to disallow nested module
> declarations, but keep in mind that some other language might be
> different.
> The whole way commands are interpreted in Verilog mode is strictly
> incorrect, but that's another topic.

I only had to modify LANG_VERILOG::parse_module. Not particularly


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