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Re: [PATCH v3 07/10] RISC-V: Add awareness for RISC-V reloations


From: Daniel Kiper
Subject: Re: [PATCH v3 07/10] RISC-V: Add awareness for RISC-V reloations
Date: Wed, 21 Nov 2018 17:31:39 +0100
User-agent: NeoMutt/20170113 (1.7.2)

On Wed, Nov 21, 2018 at 05:08:09PM +0100, Andreas Schwab wrote:
> On Nov 21 2018, Daniel Kiper <address@hidden> wrote:
>
> >> +  case R_RISCV_BRANCH:
> >> +    {
> >> +      grub_uint32_t *abs_place = place;
> >> +      grub_ssize_t off = sym_addr - (grub_addr_t) place;
> >> +      grub_uint32_t imm12 = (off & 0x1000) << (31 - 12);
> >> +      grub_uint32_t imm11 = (off & 0x800) >> (11 - 7);
> >> +      grub_uint32_t imm10_5 = (off & 0x7e0) << (30 - 10);
> >> +      grub_uint32_t imm4_1 = (off & 0x1e) << (11 - 4);
> >> +      *abs_place = (*abs_place & 0x1fff07f)
> >> +                   | imm12 | imm11 | imm10_5 | imm4_1;
> >
> > Could not we use some constants instead of numbers here?
>
> These are just where the insn encoding puts the bits.
>
> > If this does not make sense than please name the source of this numbers.
>
> https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf

OK, please add the document title and link to it into relevant source files.

Daniel



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