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Re: [PATCH] Fix 32-bit ARM handling of the CTR register

From: Daniel Kiper
Subject: Re: [PATCH] Fix 32-bit ARM handling of the CTR register
Date: Mon, 25 May 2020 14:27:16 +0200
User-agent: NeoMutt/20170113 (1.7.2)

On Mon, May 25, 2020 at 12:56:16PM +0100, Leif Lindholm wrote:
> On Sun, May 24, 2020 at 12:32:48 +0100, Marc Zyngier wrote:
> > When booting on an ARMv8 core that implements either CTR.IDC or CTR.DIC
> > (indicating that some of the cache maintenance operations can be
> > removed when dealing with I/D-cache coherency, GRUB dies with a
> > "Unsupported cache type 0x........" message.
> >
> > This is pretty likely to happen when running in a virtual machine
> > hosted on an arm64 machine (I've triggered it on a system built around
> > a bunch of Cortex-A55 cores, which implements CTR.IDC).
> >
> > It turns out that the way GRUB deals with the CTR register is a bit
> > harsh for anything from ARMv7 onwards. The layout of the register is
> > backward compatible, meaning that nothing that gets added is allowed to
> > break earlier behaviour. In this case, ignoring IDC is completely fine,
> > and only results in unnecessary cache maintenance.
> >
> > We can thus avoid being paranoid, and align the 32bit behaviour with
> > its 64bit equivalent.
> >
> > Signed-off-by: Marc Zyngier <address@hidden>
> This patch has the added benfit that it gets rid of a (gnu-specific)
> case range.
> Reviewed-by: Leif Lindholm <address@hidden>
> Thanks!

Reviewed-by: Daniel Kiper <address@hidden>


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