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[Guile-commits] 345/437: PPC: Implement and use mcrxr emulation by defau
From: |
Andy Wingo |
Subject: |
[Guile-commits] 345/437: PPC: Implement and use mcrxr emulation by default |
Date: |
Mon, 2 Jul 2018 05:14:51 -0400 (EDT) |
wingo pushed a commit to branch lightning
in repository guile.
commit a16adad0fdf37cc40804aafb124edb315fa4fad0
Author: Paulo Andrade <address@hidden>
Date: Fri Dec 26 15:41:12 2014 -0200
PPC: Implement and use mcrxr emulation by default
* lib/jit_ppc-cpu.c: Add mcrxr instruction emulation,
as this instruction has been phased out, and should be
implemented as a kernel trap.
---
ChangeLog | 6 ++++++
lib/jit_ppc-cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/ChangeLog b/ChangeLog
index eaa3134..1583aa5 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,11 @@
2014-12-26 Paulo Andrade <address@hidden>
+ * lib/jit_ppc-cpu.c: Add mcrxr instruction emulation,
+ as this instruction has been phased out, and should be
+ implemented as a kernel trap.
+
+2014-12-26 Paulo Andrade <address@hidden>
+
* lib/jit_arm.c: Better check for need to flush constants
before the pool being no longer reachable.
diff --git a/lib/jit_ppc-cpu.c b/lib/jit_ppc-cpu.c
index 81e5867..f358bfa 100644
--- a/lib/jit_ppc-cpu.c
+++ b/lib/jit_ppc-cpu.c
@@ -270,7 +270,42 @@ static void _FXS(jit_state_t*,int,int,int,int,int,int,int);
# define LD(d,a,s) FDs(58,d,a,s)
# define LDX(d,a,b) FX(31,d,a,b,21)
# define MCRF(d,s) FXL(19,d<<2,(s)<<2,0)
-# define MCRXR(d) FX(31,d<<2,0,0,512)
+# if DEBUG
+/* In case instruction is emulated, check the kernel can handle it.
+ Will only generate it if DEBUG is enabled.
+"""
+Chapter 6. Optional Facilities and Instructions that are being
+Phased Out of the Architecture
+...
+6.1 Move To Condition Register from XER
+The mcrxr instruction is being phased out of the archi-
+tecture. Its description is included here as an aid to
+constructing operating system code to emulate it.
+
+Move to Condition Register from XER
+X-form
+mcrxr BF
+31 BF // /// /// 512 /
+0 6 9 11 16 21 31
+CR(4xBF:4xBF+3) <- XER(32:35)
+XER(32:35) <- 0b0000
+The contents of XER(32:35) are copied to Condition Reg-
+ister field BF. XER(32:35) are set to zero.
+Special Registers Altered:
+CR field BF XER(32:35)
+
+Programming Note
+Warning: This instruction has been phased out of
+the architecture. Attempting to execute this
+instruction will cause the system illegal instruction
+error handler to be invoked
+"""
+ */
+# define MCRXR(d) FX(31,d<<2,0,0,512)
+# else
+# define MCRXR(cr) _MCRXR(_jit,cr);
+static void _MCRXR(jit_state_t*, jit_int32_t);
+# endif
# define MFCR(d) FX(31,d,0,0,19)
# define MFMSR(d) FX(31,d,0,0,83)
# define MFSPR(d,s) FXFX(31,d,s<<5,339)
@@ -994,6 +1029,24 @@ _FXS(jit_state_t *_jit, int o, int s, int a, int h, int
x, int i, int r)
}
#endif
+#if !DEBUG
+/*
+ * Use the sequence commented at
+ *
http://tenfourfox.blogspot.com/2011/04/attention-g5-owners-your-javascript-no.html
+ */
+static void
+_MCRXR(jit_state_t *_jit, jit_int32_t cr)
+{
+ jit_int32_t reg;
+ reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
+ MFXER(rn(reg));
+ MTCRF(128, rn(reg));
+ RLWINM(rn(reg), rn(reg), 0, 0, 28);
+ MTXER(rn(reg));
+ jit_unget_reg(reg);
+}
+#endif
+
static void
_nop(jit_state_t *_jit, jit_int32_t i0)
{
- [Guile-commits] 334/437: ARM: Correct several inconsistencies with ldrd and strd, (continued)
- [Guile-commits] 334/437: ARM: Correct several inconsistencies with ldrd and strd, Andy Wingo, 2018/07/02
- [Guile-commits] 210/437: Correct all ldst test cases., Andy Wingo, 2018/07/02
- [Guile-commits] 252/437: GNU lightning 2.0.1 release, Andy Wingo, 2018/07/02
- [Guile-commits] 327/437: Force creation of the m4 directory on a clean checkout, Andy Wingo, 2018/07/02
- [Guile-commits] 314/437: Add back files missed when reapplying patches, Andy Wingo, 2018/07/02
- [Guile-commits] 354/437: Implement the jit_arg_register_p predicate., Andy Wingo, 2018/07/02
- [Guile-commits] 381/437: Remove wrong comment after cut and paste, Andy Wingo, 2018/07/02
- [Guile-commits] 209/437: Correct float division and LX with stop code generation., Andy Wingo, 2018/07/02
- [Guile-commits] 280/437: Implement the new jit_set_code interface., Andy Wingo, 2018/07/02
- [Guile-commits] 284/437: ARM: Do not emit a nop stack adjust instruction., Andy Wingo, 2018/07/02
- [Guile-commits] 345/437: PPC: Implement and use mcrxr emulation by default,
Andy Wingo <=
- [Guile-commits] 246/437: Use the logic to workaround float NaN and Inf Hercules bug conditional, Andy Wingo, 2018/07/02
- [Guile-commits] 363/437: Correct typo, Andy Wingo, 2018/07/02
- [Guile-commits] 383/437: ia64: Implement cache flush., Andy Wingo, 2018/07/02
- [Guile-commits] 371/437: Correct read of freed memory, Andy Wingo, 2018/07/02
- [Guile-commits] 342/437: x86: Implement support for the x32 abi, Andy Wingo, 2018/07/02
- [Guile-commits] 416/437: Build and pass all tests on 32 and 64 bit sparc, Andy Wingo, 2018/07/02
- [Guile-commits] 400/437: Correct missing jit_unget_reg calls, Andy Wingo, 2018/07/02
- [Guile-commits] 418/437: Correct typo and values in jit_sparc-sz.c, Andy Wingo, 2018/07/02
- [Guile-commits] 359/437: ARM: Regenerate size table for hard float armv7 or newer., Andy Wingo, 2018/07/02
- [Guile-commits] 396/437: Move definition of jit_va_ codes, cosmetic change., Andy Wingo, 2018/07/02