03/06: gnu: yosys: Update source and home-page URLs.

[guix-commits]

cbaines pushed a commit to branch master
in repository guix.

commit 535c61ccc31ff5910649225311f545e042b66c63
Author: Simon South <simon@simonsouth.net>
AuthorDate: Sun Jan 8 13:31:27 2023 -0500

    gnu: yosys: Update source and home-page URLs.
    
    * gnu/packages/fpga.scm (yosys)[source]: Update source-repository URL.
    [home-page]: Update URL.
    
    Signed-off-by: Christopher Baines <mail@cbaines.net>
---
 gnu/packages/fpga.scm | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index a516e4dc7e..066c56401a 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -141,7 +141,7 @@ For synthesis, the compiler generates netlists in the 
desired format.")
     (source (origin
               (method git-fetch)
               (uri (git-reference
-                    (url "https://github.com/cliffordwolf/yosys";)
+                    (url "https://github.com/YosysHQ/yosys";)
                     (commit (string-append "yosys-" version))
                     (recursive? #t))) ; for the ‘iverilog’ submodule
               (sha256
@@ -223,7 +223,7 @@ For synthesis, the compiler generates netlists in the 
desired format.")
            abc))
     (propagated-inputs
      (list z3)) ; should be in path for yosys-smtbmc
-    (home-page "http://www.clifford.at/yosys/";)
+    (home-page "https://yosyshq.net/yosys/";)
     (synopsis "FPGA Verilog RTL synthesizer")
     (description "Yosys synthesizes Verilog-2005.")
     (license license:isc)))