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[Help-gnucap] Time step control

From: a r
Subject: [Help-gnucap] Time step control
Date: Sun, 17 Feb 2008 01:24:01 +0000


Last time I tried Gnucap (in November) I thought I've finally managed
to make its time step control working but it looks like I haven't
tested it well enough. I would appreciate any ideas how to improve it.


1. Using euler method:

With following options my simulation runs (although waveforms are
slightly distorted, see: 1a)
.option method=euler dtmin=1e-15 abstol=1e-13 vntol=1e-7 chgtol=1e-15
reltol=1e-5 itl3=4 itl4=20 trstepgrow=1.5 trtol=0.1

Tightening time step (itl4=10):
.option method=euler dtmin=1e-15 abstol=1e-13 vntol=1e-7 chgtol=1e-15
reltol=1e-5 itl3=4 itl4=10 trstepgrow=1.5 trtol=0.1

improves results (waveforms are smoother) but the simulation fails with:
very backward time step
convergence failure, reducing (itl4)
newtime=8.009999e-09  rejectedtime=8.010000e-09  oldtime=8.009999e-09
tried everything, still doesn't work, giving up

Odd, isn't it? There is nothing special in the circuit to make it fail
at this time (it happens either with inductors included or removed
from the circuit, see: 2b). I am using my modified bm_pulse model here
so this error may be related to its event scheduling.

1a. trstepgrow settings

If I do not limit trstepgrow to 1.5, the simulation tends to take far
too large steps. In fact circuit state is calculated only at time
points forced by independent voltage source transitions. Limiting
trstepgrow "fixes" this behaviour by slowing down the process of
increasing time step, so if there is some activity immedately
following an independent voltage source transition there is a chance
it will be simulated accurately. Unfortunately when the circuit
activity occurs spontaneously of after some time from the most recent
independent voltage source transition the time step happens to b.

It makes me thinking that there is nothing in device models (bsim_310
here) that would decrease time step when the device state is not

2. Using trap method:
.option method=trap dtmin=1e-16 abstol=1e-13 vntol=1e-7 chgtol=1e-15
reltol=1e-4 trtol=0.001

2a. I get a lot of following warnings (bsim310 devices):
storage element step control error:xtr.xn3.Mn 7.24208e-19
using Euler, disabling time step control

AFAIR, there were no such warnings when I tried gnucap-20071121.

2b. If there is an inductor element in the design (a series LR
connection modeling a wire) the time step control becomes very
unstable - very small time steps, numerical oscillations. I am pretty
sure these oscillation do not come from the design (all second order
circuits are strongly damped). Removing inductors solves this
numerical stability problems.

I can reduce the amount of these oscillations by using default
simulationoptions (.option method=trap) i.e. by relaxing some
tolerances. It does not solve my problem though, as numerical
oscillations still force a small and constant time step.


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