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[Help-gnucap] testing verilog netlist input
From: |
John Griessen |
Subject: |
[Help-gnucap] testing verilog netlist input |
Date: |
Mon, 09 Feb 2009 00:53:32 -0600 |
User-agent: |
Mozilla-Thunderbird 2.0.0.17 (X11/20081018) |
Hi,
I'm attempting to follow along paralleling the example amp from
http://wiki.gnucap.org/dokuwiki/doku.php?id=gnucap:languages:verilog.
I can include the below OK. Then I can type an instantiation of it in verilog
syntax
as if the gnucap-verilog command line is a "top level module" as defined in
section 6.1 of verilog-ams_2.3_aug08.
verilog netlist to include:
==================================================
module verilog_io ( GND , OUT , IN );
// Port directions begin here
inout GND ;
inout OUT ;
inout IN ;
// Wires from the design
electrical B ;
electrical GND ;
electrical OUT ;
electrical IN ;
// continuous assignments
// Package instantiations
capacitor #(.c(1250e-9) ) C1 ( .p(B), .n(GND));
inductor #(.l(.001) ) L1 ( .n(OUT), .p(B));
resistor #(.r(1000) ) R1 ( .n(B), .p(IN));
endmodule
=================================
gnucap-verilog>list
// structural Verilog generated by gnetlist
// WARNING: This is a generated file, edits
// made here will be lost next time
// you run gnetlist!
// Id ..........$Id$
// Source.......$Source$
// Revision.....$Revision$
// Author.......$Author$
module verilog_io (GND,OUT,IN);
// Port directions begin here
// Wires from the design
// continuous assignments
// Package instantiations
capacitor #(.c( 1.25u)) C1 (.p(B),.n(GND));
inductor #(.l( 0.001)) L1 (.p(B),.n(OUT));
resistor #(.r( 1.K)) R1 (.p(IN),.n(B));
endmodule // verilog_io
verilog_io #() U1 (.GND(0),.OUT(out),.IN(in));
verilog_io #() U1 (.GND(0),.OUT(out),.IN(in));
So, next I'm going to try spice mode to enter a vsource.
Is that the way to do it now? If so, should I keep in spice mode and follow an
example of spice simulation
to do a run?
Will try that first thing in AM.
John Griessen
--
Ecosensory Austin TX
- [Help-gnucap] testing verilog netlist input,
John Griessen <=