Re: Re[2]: [Help-gnucap] Verilog-A(MS) & gnucap

[Leandro Marsó]

2011/2/9  <address@hidden>:
> Hello Leandro,
>
>
> from what I saw in available sources, likely "input" and "output" are not
> implemented.
>
> What I saw - you can use "inout" and define nodes, not ports.
>
> so - pls try:
>
>  module vamp (in, out) ;
>  inout in, out ;
>  electrical in, out ;
>
> ...
>  V(out) <+ GAIN_V * V(in) ;
> ...
>
> regards
> Gena
Hi Gena,
I've tried that but it yields exactly the same error. Thank you anyway.
Best regards,
Leandro