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Re: gnu make

From: Paul D. Smith
Subject: Re: gnu make
Date: Tue, 7 May 2002 09:21:33 -0400

%% address@hidden writes:

  jk> > cat makefile 
  jk> include 

  jk> %.o: %.c 
  jk>   echo "Compiling" 
  jk>   gcc -c  $< -o $@ 

  jk> SRCS = t.c 

  jk> > cat 
  jk> OBJ = $(SRCS:.c=.o) 

  jk> lib : $(OBJ) 
  jk>   echo $(SRCS) 

So, after the include your makefile looks like this:

  OBJ = $(SRCS:.c=.o) 

  lib : $(OBJ) 
        echo $(SRCS) 

  %.o: %.c 
        echo "Compiling" 
        gcc -c  $< -o $@ 

  SRCS = t.c 

The problem is that SRCS is not defined yet when OBJ is used as a
prerequisite of the lib target, so $(OBJ) resolves to the empty string.

 Paul D. Smith <address@hidden>          Find some GNU make tips at:            
 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist

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