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Re: Loops in makefile

From: Boris Kolpackov
Subject: Re: Loops in makefile
Date: Thu, 10 Jul 2003 15:44:15 +0000 (UTC)
User-agent: nn/6.6.5+RFC1522

address@hidden writes:

> I have a variable from which my target names are derived, for example 
> listvar = a b c p l w q x y 
> The targets are made as follows 
> apnd.t : apnd.s a.h
> bpnd.t : bpnd.s b.h
> .
> .
> xpnd.t : xpnd.s x.h
> ypnd.t : ypnd.s y.h 
> Is there any way I can loop through $(listvar) in the makefile instead of 
> explicitly writing them all out? 

How about something like this:

listvar := a b c

.PHONY: all
all : $(listvar)

define Rule
$(1):; @echo $$@

$(foreach target,$(listvar),$(eval $(call Rule,$(target))))

Also you may want to look at the documentation of $(foreach ), $(call ) and


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