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Re: Multiple make-ing. Please help.

From: Boris Kolpackov
Subject: Re: Multiple make-ing. Please help.
Date: Tue, 15 Jul 2003 19:13:14 +0000 (UTC)
User-agent: nn/6.6.5+RFC1522

Andrea Riciputi <address@hidden> writes:

>       SourceDir/
>                       *.c
>                       *.h
>                       makefile
>                       ObjectDir/
>                                       *.o
>                                       *.lo
>                                       *.exe
>                                       *.so
>                       WrapperDir/
>                                       *.i
> The "makefile" and "" files are adapted from Paul's site 
> examples, all the object files are placed in the "ObjectDir", while the 
> inteface files for the wrapper are placed in the "WrapperDir". The 
> wrapper uses the .i file to create a .c file with the wrapping code. 
> Obviously the resulting wrapping code must be placed in the "SourceDir" 
> along with all the other .c files.
> My intention is to check for .i files before starting gcc compilation. 
> When any of the .i files is newer than the wrapping code make should 
> call the wrapper create the new wrapping code, put it in the 
> "SourceDir" and after that call gcc. 

I would approach this as follows:

(1) create SourceDir/Makefile.wrapper which generates .c from .i and 
    look something like this:

.vpath: %.i WrapperDir

# wc stands for 'wrapper compiler' and not what you thought ;-)
%.c : %.i
        wc -o $@ $<

.PHONY: all
all : foo.c bar.c

(2) create SourceDir/ObjectDir/Makefile that compiles your so/exe

(3) create SourceDir/Makefile that invokes make on 
    SourceDir/Makefile.wrapper and SourceDir/ObjectDir/Makefile in right


.PHONY: _submodules


target_directory_list := ObjectDir
target_makefile_list  := Makefile.wrapper

ObjectDir : Makefile.wrapper

.PHONY: $(target_directory_list) $(target_makefile_list)

_submodules:: $(target_directory_list) $(target_makefile_list)

        $(MAKE) -C $@ $(MAKECMDGOALS)

        $(MAKE) --no-print-directory -f $@ $(MAKECMDGOALS)

# These rules keep make from trying to use the match-anything rule below to
# rebuild the makefiles.
Makefile : ; :: ;
%.rules :: ;

# Anything we don't know how to build will use this rule.  The command is a
# do-nothing command, but the prerequisites ensure that the appropriate
# recursive invocations of make will occur.
% :: $(target_directory_list) $(target_makefile_list) ;


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