Re: How can I generate rules automatically in make?

[Paul D. Smith]

%% address@hidden writes:

  hpvl> As mentioned below I try to generate some rules in MAKE to
  hpvl> define dependencies.  Can someone help me out here?  I tried a
  hpvl> suggestion from Paul smith but I can't get this working, maybe I
  hpvl> missed something?

Did you look at the contents of the generated.mk file?  Did it look
correct to you?

  hpvl> MODULES=aa bb 
  hpvl> MOD_PATH = $(foreach OBJ,$(MODULES),../../$(OBJ)/process) 

  hpvl>   generated.mk:  Makefile
  hpvl>        rm -f $@
  hpvl>        for t in $(MOD_PATH); do \
  hpvl>          echo "$$t/gen.out : $$(wildcard $$t/cmd/*.tcl)" >> $@; \

The "echo" line above seems wrong to me.  If you're going to get
$(wildcard ...) in the output it seems like you need to escape it to the
shell, like this:

       echo "$$t/gen.out : \$$(wildcard $$t/cmd/*.tcl)" >> $@; \
                           ^
Note the added backslash above.

  hpvl> This construction has to work for parallel runs too!. 
  hpvl> From the manual it is suggested to use .PHONY. 

I think you're misreading the manual.  In this case, since you're not
invoking make recursively in subdirectories, you don't need .PHONY
(indeed you certainly don't _want_ it or your make will recurse
forever!)

All you need to do for parallel builds is make sure all your
dependencies are properly declared.

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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