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a little trick about making programs that makes variables...

From: Paolo Gai
Subject: a little trick about making programs that makes variables...
Date: Thu, 08 Jan 2004 16:29:25 +0100


I'm currently having the following problem that I cannot solve; it is
basically related to how make compile a program that is then used in a
expansion of a prerequisite of another rule.

I found a solution, but I feel it is not so elegant, and I wonder if
someone has better thoughts than me...

Here is an abstract version of the problem, that requires only make,
cat, cp, rm and echo:

myvar = $(shell cat goofy)

all: goofy2
        make -C . test

        rm goofy goofy2

test: $(myvar) goofy
        @echo "end... did the Done message has been printed?"

        @echo Done!!!

goofy: goofy2
        cp goofy2 goofy

        echo mygoofy > goofy2

the problem is in the rule "test". In fact, myvar depends on the
existence of the file goofy, that does not exist.

When executed the first time, goofy will be created -after- the
expansion of myvar. When executed the second time, the makefile will
work, printing "Done!!!".

I currently found a workaround for that that replaces the test rule with
the following two rules:

test: goofy
        make -C . test2

test2: $(myvar)
        @echo "end... did the Done message has been printed?"

...the question there a way to do that without using 
"make -C . test2"



Paolo Gai - ReTiS Lab - PhD Student

Scuola Superiore S. Anna        Tel       : +39 050 883 451 
Polo S. Anna Valdera            Fax       : +39 050 883 452
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