Re: static pattern variables, bug or feature ?

[Greg Chicares]

Benoit Poulot-Cazajous wrote:
> 
> Consider this Makefile :
> 
> toto: toto.o
> toto: CFLAGS=-g
> %.o: %.c
>         gcc -o $@ -c $< $(CFLAGS)
> %: %.o
>         gcc -o $@ $<
> 
[move example below for discussion]
> So, it looks like variable definitions in static patterns can "propagate"
> to dependencies. While it can be useful, it is also quite confusing.
> Is it a bug, that may be fixed one day, or a feature that we can rely on ?

The "Target-specific Variable Values" section of the make manual
discusses this. As I read it, it says this is a feature:
  "when you define a target-specific variable, that variable value
  is also in effect for all prerequisites of this target"

> If I run 'make toto toto.o', I get :
>         gcc -o toto.o -c toto.c -g
>         gcc -o toto toto.o

Target 'toto' is made, with 'CFLAGS=-g' in effect for its
prerequisite 'toto.o'. Then there's nothing left to do for
the other target specified on the command line.

> but 'make toto.o toto' gives :
>         gcc -o toto.o -c toto.c
>         gcc -o toto toto.o

Target 'toto.o' is made, with no particular $(CFLAGS).
Then there's nothing left to do for the other target
specified on the command line.