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multiple prerequisites in pattern rules

From: Rolf Sandau
Subject: multiple prerequisites in pattern rules
Date: Thu, 29 Jan 2004 11:46:17 +0100

Following "Recursive Make Considered Harmful"  Peter Miller and Paul D.
Smith, "Advanced Auto-Dependency Generation" I created a Makefile that
generates the dependencies of c-sources (%.P) when compiling the c-source.
While avoiding re-exec of make, if dependency file does not exist and
avoiding 'no rule to make target ...' if a prerequisite is removed there is
still a problem left.
If anyone kills just dependency-files, make wouldn't do anything, but I
would prefer make to recompile and regenerate dependencies. For I couldn't
find anything that helps, in my typical naive way I just tried a second
prerequisite-pattern :
      %.o: %.c %.P
... and what a surprise, it worked with my cygwin's gnu-make 3.80 :-)

Now the questions:
Is this a legal construction and should it work with other gnu-makes on
other platforms too?
And if it's neither legal nor globally available, does anybody now a way to
fix the problem?
On the other hand, if everything is correct, does exist a documentation
about this?



SRCS := main.c


# determine the object files
OBJS := ${patsubst %,${OBJDIR}/%,${patsubst %.c,%.o, ${filter
DEPS := ${patsubst %.o,%.P,${OBJS}}

MAKEDEPEND = gcc -M $< > ${basename address@hidden
COMPILE.c := gcc ${CFLAGS}

proj: $(OBJS)

${OBJDIR}/%.o: %.c ${OBJDIR}/%.P
      cp ${basename address@hidden ${basename address@hidden; \
      sed -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
          -e '/^$$/ d' -e 's/$$/ :/' < ${basename address@hidden >> ${basename
      rm -f $*.d
      ${COMPILE.c} -o $@ $<


-include $(OBJS:%.o=%.P)

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