Re: Executing a shell script in a Makefile

[G2345C]

wow ... Thanks for the tips ... i learn more stuff
every day ..
i think i found where the problem is but can't get it
to work yet


all ::
        if [ -r $(GPS_ENGINE_MANIFEST) ] ; then \
           cd $(BUILD_DIR) && $(SHELL) ./copfile.sh ;
\
        fi 
        cd $(GPS_ENGINE_OBJS_DIR) && \
           $(LIBTOOL) $(LIBTOOL_LINK_TAG) $(GCC) -o
libtest.la \
              $(wildcard $(GPS_ENGINE_OBJS_DIR)/*.lo)
-rpath $(INSTALL_LIB_DIR) ; \
        else \
         .....
        fi

the $(wildcard $(GPS_ENGINE_OBJS_DIR)/*.lo) is not
expended properly... it's empty the first time i ran,
but it i run the make file the second time it expend
all the .lo files properly ... what cause this
problem?

thanks

--- "Paul D. Smith" <address@hidden> wrote:

> %% G2345C <address@hidden> writes:
> 
>   g> all :
>   g>    if [ -d $(GPS_ENGINE_OBJS_DIR) ] ; then \
>   g>       for f in `cd $(GPS_ENGINE_OBJS_DIR) &&
> ls` ; do
>   g> \
>   g>          case $$f in \
>   g>            *.lo)     HB="$(HB) `echo $$f`" ;; \
>   g>            *)        ;; \
>   g>          esac ; \
>   g>       done \
>   g>    fi 
>   g>    echo $(HB)
> 
>   g> I want to put all of the file that name is *.lo
> into a
>   g> string $(HB) how do I do that
> 
>   g> Right now it echo empty string $(HB)
> 
> You have to be very careful to distinguish between
> SHELL COMMANDS and
> MAKE COMMANDS.  In general any line that starts with
> a TAB is passed to
> a shell to be executed there, it's NOT executed by
> the make program.
> Obviously, a shell script cannot modify the contents
> of a make variable
> directly!  That just can't work.  So this:
> 
>    *.lo)     HB="$(HB) `echo $$f`" ;; \
> 
> is not doing what you think it is.  First the make
> variable reference
> $(HB) is expanded and resolves to the empty string. 
> Then the entire
> thing is handed to the shell, so when the shell sees
> it the line looks
> like this:
> 
>    *.lo)     HB=" `echo $$f`" ;; \
> 
> (you can see this for yourself if you look at the
> output make prints).
> 
> This is of course a very complicated way to just
> say:
> 
>    *.lo)     HB=" $$f" ;; \
> 
> (the echo just prints the value after all).
> 
> And this, remember, is setting the SHELL variable
> HB, not the MAKE
> variable HB.
> 
> 
> The next thing to remember is that every logical
> line in a command
> script is invoked in a separate shell.  So, after
> the if statement where
> you don't have a backslash:
> 
>       done \
>    fi 
>    echo $(HB)
> 
> that first shell is done and exits, then a new shell
> is started to run
> the echo command.
> 
> Well, when the first shell exits the SHELL variable
> HB is gone; it
> existed only in the memory of that shell.  Now the
> next line you invoke
> a new shell and pass the expansion of the MAKE
> variable HB, which is
> still set to nothing, and it echos the empty string.
> 
> -- 
>
-------------------------------------------------------------------------------
>  Paul D. Smith <address@hidden>          Find some
> GNU make tips at:
>  http://www.gnu.org                     
> http://make.paulandlesley.org
>  "Please remain calm...I may be mad, but I am a
> professional." --Mad Scientist
> 


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