Re: Dependency to generated list of source files

[Paul D. Smith]

%% <address@hidden> writes:

  ds> srcs_file := srcs.txt
  ds> srcs = $(shell cat $(srcs_file) 2>/dev/null)
  ds> objs = $(srcs:%.c=%.o)

  ds> $(srcs_file) :
  ds>   for f in foo.c bar.c; do touch $$f; echo $$f >> $@; done

Very confusing.  I'm assuming you have a good reason for doing things
this way.

  ds> The problem is, that only the second invocation of 'make' builds
  ds> the targets specified in 'objs'. This is probably because during
  ds> the first invocation the variable 'objs' has no value.

  ds> Is there a way to avoid two invocations of make?

If you want to do things this way you have two choices:

 1) Auto-generate a makefile, then include it.  When the makefile is
    rebuilt, make will automatically re-exec itself.  While technically
    this involves two invocations of make, the user only types "make"
    once and only knows it ran once.

      include srcs.mk

      srcs.mk: srcs.txt
            rm -f $@
            for f in `cat $<`; do \
              echo "srcs += $$f" >> $@; \
            done

      objs = $(srcs:%.c=%.o)

    This will work with any version of GNU make.

 2) If you're willing to require GNU make 3.80, you can use $(eval ...).
    This avoids an extra recursion.

-- 
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