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How can I avoid duplication of code in makefiles?
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From: |
Angel Tsankov |
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Subject: |
How can I avoid duplication of code in makefiles? |
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Date: |
Fri, 12 Aug 2005 17:42:10 +0300 |
I've noticed that some of my makefiles differ only in:
output file name;
extension of source files;
compiler that is to be invoked;
compiler options;
All the rest is the same - variables, functions and targets.
Provided this, how can I reduce duplication of code in makefiles?
Angel Tsankov
address@hidden
- How can I avoid duplication of code in makefiles?,
Angel Tsankov <=