Re: Request for help in setting a variable in GNU Make.

[Louie McCrady]

Wow!

Thank you all for your excellent and timely responses to my request.

The advice I got from Alexandre Girao:

        $(eval sourceFiles += $<)

does what I was looking for.  I am intrigued by the other suggestions.
I will investigate them further and let you know how they work for me.

Thank you all again very much for your help.

Sincerely,

Louie McCrady


Here is a little more background on what I am trying to accomplish with
my Makefile if you are interested.  

I have a project that contains hundreds of files.  On an average build,
40 or more of these files will be recompiled.  If certain header files
are touched, this number can be several hundred.

This is normally handled in the base Makefile with a command like this:

%.o : %.cpp
        @echo "Building C++ Object: $@"
        @$(CXX) -c $(MMD_STRING) $(CXXFLAGS) $(OBJ_CXX_FLAGS) $(OPTIMISE)
$(includeArgs) -o $@ $<

Which invokes g++ for each .cpp file.  I thought I might be able to
speed up the compile process if I accumulated the necessary .cpp files
into a string and passed them to g++ at one time.  This should at least
eliminate the need to load up g++ for each file.

Now this part of the base Makefile becomes:

%.o : %.cpp
        $(eval sourceFiles += $<)

Then, someplace in the file I have to invoke g++ with $(sourceFiles).
I've done this with other make systems and compilers and it seems to
work well.  

I don't know enough about how g++ works yet, but hopefully it is able to
hold some of the standard C++ information between file compilations.

Eventually, I would like to work in some pre-compiled headers, and
incremental linking.

I'm always interested in learning more about make techniques, and I will
try some of the other suggestions.  I'm a minimalist at heart, and I'm
always looking for ways to streamline the build process.  I appreciate
all of your suggestions. They are very interesting to me.