Re: Expanding a variable in the dependencies

[Kristof Provost]

On 2007-07-18 22:41:26 (+0300), Or Goshen <address@hidden> wrote:
> Hi
> 
> I have the following make file:
> 
> TEST_LO=test.lo
>  
> %.so: $($*_LO)
>         $(CC) $(LDFLAGS) -shared -Wl,-soname,$*.so.0 -o $*.so $($*_LO)
>  
> %.lo: %.c
>         $(CC) $(CFLAGS) -fPIC -o $*.lo -c $*.c
> 
> 
> When I execute "make TEST.so" I get:
> 
> $ make TEST.so
> gcc -shared -Wl,-soname,TEST.so.0 -o TEST.so test.lo
> gcc: test.lo: No such file or directory
> make: *** [TEST.so
> ] Error 1
> 
> My question is - why doesnt it expand "$($*_LO)" in the dependencies as well ?
> (I got the file "test.c" in the directory)
 
Make will determine prerequisites based on the variable value when the
line is parsed, not when the target is built. That means make isn't
aware that test.lo is a prerequisite. Try putting '@echo prereqs: $^' 
before the compile statement in the %.so rule.

Fortunately GNU Make has .SECONDEXPANSION.
Read the manual, specifically this bit:
http://www.gnu.org/software/make/manual/make.html#Secondary-Expansion

You can rewrite your makefile to become:

.SECONDEXPANSION:

TEST_LO=test.lo

%.so: $$($$*_LO)
    $(CC) $(LDFLAGS) -shared -Wl,-soname,address@hidden -o $@ $^

%.lo: %.c
    $(CC) $(CFLAGS) -fPIC -o $@ -c $<


Kristof