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From: Bryan Ischo
Subject: Eureka
Date: Thu, 3 Jan 2008 19:26:45 -0500 (EST)
User-agent: SquirrelMail/1.4.8-4.fc5

I think I have made some fundamental realizations about what GNU Make is
doing in my example that helps me to clarify some things.

If my PROCESS_FRAGMENT template were instead defined as:


-include $(1).mk

$(call TEST_RULE,$(1),$(VARIABLE))


Then the problem is that I am expecting VARIABLE, when set via the
-include of $(1).mk, to be used when evaluating the inner $(call) of the
TEST_RULE template.  But what I didn't realize was that $(VARIABLE) is
expanded as part of the expansion of the text of the entire template,
which happens *before* the "-include $(1).mk" directive is processed by
GNU Make as makefile text (which itself only happens because the outer
$(eval) function instructs GNU Make to do so).  So as a result,
$(VARIABLE) contains *nothing* when the template is being expanded, which
is not what I wanted.

The subtle problem is that the evaluation of the $(call) tries to replace
all variable references and function calls *before* the outer $(eval) even
gets a chance to execute the -include directive that would supply values
to be used when the $(call) is evaluated.

I am still trying to think of a way around this than is better than what I
eventually came up with.  What I eventually came up with was this:


-include $(1).mk

$$(eval $$(call TEST_RULE,$(1),$$(VARIABLE)))


This only worked because I was preventing the expansion of the outer
$(call) function from further expanding the inner $$(VARIABLE) reference
and $$(call) function, thus preventing the premature subtitution of the
value of $(VARIABLE).  And I had to add an $$(eval) to wrap around it
because otherwise the outer $(eval) would evaluate this, resulting in some
text which wasn't then itself evaluated.

Is there a better solution?


Bryan Ischo                address@hidden            2001 Mazda 626 GLX
Hamilton, New Zealand     RedHat Fedora Core 5

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