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Rule-specific variables

From: Brendan Heading
Subject: Rule-specific variables
Date: Mon, 10 Mar 2008 17:56:46 +0000

Hi all, I've got a Makefile which is something like this :
define compile_c
#Stuff which compiles a C file
define compile_c++
#Stuff which compiles a C++ file
%.o : %.c
%.o :
$(compile_cc) There's lots of duplication within compile_c and compile_cc macros (and there are a lot more of these), so I'd like to reduce them to one macro, and use variables to control their behaviour. I tried this :
$.o : $.c
$(compile)C I didn't think this work, and I was right. If I recall correctly, GNU make invokes a new shell process for each line, so setting variables won't work. Target/Rule-specific variables won't work either, as I've got a mix of C and C++ files so the variable only gets set once (when the Makefile is parsed). Are there any other ways to solve this ? (and yes, if you're thinking "why the hell's he doing all that ?" you'd be quite justified. Trying to make an existing horrible set of Makefiles workable, and a rewrite isn't an option .. ) regards Brendan

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