Re: some questin about Makefile

[Greg Chicares]

On 2009-09-16 13:46Z, loody wrote:
[...]
> SRCDIR    = $(ROOT) ./device/display ./device/fatfs ./device/misc
> VPATH = ${SRCDIR}
[...]
> OBJ_C = cpufunc.o Interrupt.o main.o memtst.o ntsys.o Display.o
> diskio.o FileSystem.o tff.o misc.o
> OBJ = cpufunc.o Interrupt.o main.o memtst.o ntsys.o Display.o diskio.o
> FileSystem.o tff.o misc.o
> 
> .PHONY : all clear depend
> all: $(OBJ)
> $(OBJ_C) : %.o : %.c
>         @echo OBJ_C=$(OBJ_C)
>         @echo prerequisite = $<
>         @echo target = $@
>         $(CC) $(CFLAGS) -c $<
[...]
> my question are:
> 1. what does the pattern rule of "OBJ_C : %.o : %.c" mean?

Actually, it's
> $(OBJ_C) : %.o : %.c
which is virtually identical to the first example discussed in the
  "Syntax of Static Pattern Rules"
section of the make manual.

> 2. I purposely assign the member of OBJ_C without directories, but why
> the output of $< still has directories?

Because this:
> VPATH = ${SRCDIR}
tells 'make' where to find prerequisites. For example:

> SRCDIR    = $(ROOT) ./device/display ./device/fatfs ./device/misc
> prerequisite = ./device/fatfs/tff.c

prerequisite file 'tff.c' was found in './device/fatfs/'.

> 3. the prerequisite of all is $(OBJ), but why make find $(OBJ_C) as
> the prerequisite for execution?

Those two variables happen to be defined identically.