Target with fake dependencies

[Beber]

Hi,

I'm trying to wrote a generic Makefile that will have to do what I ask
in all SUBDIRS (declared inside Makefile). For exemple :

$ make pdf odt
make -C ni_a_gomz_brezhoneg pdf odt
...
make -C troit_e_brezhoneg pdf odt

$ make pdf dummy-target
make -C ni_a_gomz_brezhoneg pdf dummy-target
make[1]: Entering directory `/home/beber/bzh/skol_ober/ni_a_gomz_brezhoneg'
make: *** No rule to make target `dummy-target'.  Stop.

I actually did this like that :

---
SUBDIRS = \
        ni_a_gomz_brezhoneg \
        troit_e_brezhoneg

all:    $(SUBDIRS)

%:
        @for DIR in $(SUBDIRS) ; do \
                echo $(MAKE) -C $$DIR $@ ; \
                $(MAKE) -C $$DIR $@ ; \
        done

.PHONY: $(SUBDIRS)
---

This is ok when I use :
  - make all
  - make clean
  - make dummy-target

Not important : I can't get it make go in the subdir with all previous target as
argument. I get the following scheme :

$ make pdf odt
make -C ni_a_gomz_brezhoneg pdf
..
make -C troit_e_brezhoneg pdf
..
make -C ni_a_gomz_brezhoneg odt
..
make -C troit_e_brezhoneg odt
..

This is also fine.

But, I can't just build one of the subdir, if I ask just
ni_a_gomz_brezhoneg target for exemple :

$ make ni_a_gomz_brezhoneg
make: Nothing to be done for `ni_a_gomz_brezhoneg'.

Also I can override this :
$ make -C ni_a_gomz_brezhoneg
make: Entering directory `/home/beber/bzh/skol_ober/ni_a_gomz_brezhoneg'

This is not a worry, but i'd like to understand why there is nothing to
do as it's .PHONY.

Another thing is that I'd like to avoid the "shell for loop". foreach is
not really appropriate as it make things less visibles by executing at
once.

I did this like that in past for file like :

---
SRC     = \
          br.po

OBJMO   = $(SRC:po=mo)

# Build
%.mo %.gmo:     %.po
        $(MSGFMTPRG) $(MSGFMTOPT) -o $@ $<

# Install
install: $(OBJMO)
        $(MAKE) $(addprefix install-, $^)

install-%.mo:   $(OBJMO)
        $(INSTALLPRG) $(INSTALLOPT) $< $(localedir)/$*/LC_MESSAGES/$(NAME).mo
---

I don't known if it's a good practice, but it permit me to avoid "shell loop"
by re-executing make and redefined target on the fly :

$ make install prefix=/tmp
make install-br.mo install-fr.mo

I'm trying to achieve the same thing when I have to use $(MAKE) -C to
go inside subdir as demonstrated previously.

Thanks for your advice
Beber

And sorry for the bad english.

-- 
Beber

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