Re: Why does redirecting to other makefile execute rules differently?

[Philip Guenther]

On Tue, Feb 9, 2010 at 6:15 AM, Timo Suoranta
<address@hidden> wrote:
> Short story: "make test1" executes rules twice, why? "make test2" works as
> expected.

Because your .DEFAULT rule violates rule #2 listed here:
    http://make.paulandlesley.org/rules.html


> Long story: I'm trying to have a generic Makefile that detects platform
> using uname and then forwards goals to another Makefile.b. But I am getting
> targets being built multiple times. This happens when the target Makefile.b
> calls $(MAKE). Currently these $(MAKE) commands do not specify makefile, and
> I'd like to keep it that way. So they go to the default Makefile after which
> they come back to Makefile.b. But why do rules get executed twice?
>
>
> # Makefile
>
> .DEFAULT:
>        $(MAKE) -f Makefile.b $(MAKECMDGOALS)

.DEFAULT says "for *each* target that doesn't have a matching rule,
use this rule".  So, when you invoke make with multiple targets, that
command gets invoked *for each of them*.  When you invoke "make foo
bar", it's like the Makefile contained

foo:
        $(MAKE) -f Makefile.b $(MAKECMDGOALS)
bar:
        $(MAKE) -f Makefile.b $(MAKECMDGOALS)

It decides to build 'foo' and invokes the command "make -f Makefile.b
foo bar", then it decides to build 'bar' and invokes the command "make
-f Makefile.b foo bar".  So the solution is to follow rule #2 and
instead of passing $(MAKECMDGOALS), just pass address@hidden


That said, this design seems needlessly inefficient.  Instead of
recursively invoking with the correct makefile, why not just 'include'
that makefile?

Every time you recursively invoke make to do something, you
effectively tell make "for *this* target, forget everything you know,
flush the directory cache, ignore that you've already determined that
various files don't need to be built; if the question arises, do that
work all over again!"  It's like people are afraid their build systems
will be too fast.


Philip Guenther