Re: simple pattern rules

[Paul Smith]

On Tue, 2010-04-06 at 10:41 -0700, Payal wrote:
> On Tue, Apr 06, 2010 at 03:12:11PM +0200, Stephan Beal wrote:
> > On Tue, Apr 6, 2010 at 3:00 PM, Greg Chicares <address@hidden>wrote:
> > 
> > > # How to build it (if necessary).
> > > %.cdb : %.tcp
> > >        tcprules $@ $*.tcp.tmp < $^
> > >
> > 
> > A slight addendum to that: pattern rules will never be invoked
> > "automatically" - there must be a named rule which refers to them. e.g. Make
> > has lots of built-in pattern rules, but none of them will activate unless
> > you actually name a file which resolves to one of the rules.
> 
> Can someone please explain the above in bit more detail? I am having a
> hard time understanding anything about pattern rules.

Realize that make will NEVER just go out into your directory looking for
things it might know how to build.  That's just not the way it works.
The only things make will ever build are things you have explicitly
asked it to build.

How do you explicitly ask it to build something?  One way is to put a
target on the command line, like:

        make foo.cdb

Now make has a goal: foo.cdb.  Next it says how do I build that thing?
First it looks for an explicit rule that says how to do it and if one
exists:

        foo.cdb: foo.tcp ; tcprules $@ $*.tcp.tmp < $^

then it will use that.  If no explicit rule exists, then make will look
for an implicit rule.  There are two types of implicit rules: suffix
rules and pattern rules.  Suffix rules are standard (described in POSIX)
so they're more portable, but they're harder to use and understand and
much less flexible, so generally we don't use them unless you need your
makefile to work with non-GNU versions of make.

That leaves pattern rules, like you have defined.  This doesn't tell
make "go find every .tcp file and turn it into a .cdb file".  What it
tells make is, "if you want to build a .cdb file, and you can find
a .tcp file, then here's a rule you can use to create the former
(typically using the latter)".


Of course, adding everything to the command line all the time is a pain.
So, if you don't specify anything on the command line then make looks
for the first explicit (not pattern) target in the makefile, and builds
that.

By convention, but not requirement, the first target in the makefile is
often called "all".  Make will try to build "all" and in order to build
"all" it first needs to try to build all the prerequisites of "all",
etc. etc.

So, if you have a list of targets you want built when a user runs "make"
by itself, they have to be a prerequisite of the first target (or a
prerequisite of a prerequisite of the first target, etc.)