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Re: #include in a C file

From: Björn Michaelsen
Subject: Re: #include in a C file
Date: Sat, 4 Dec 2010 22:52:05 +0100

Hi Ali,

Am Sat, 4 Dec 2010 14:00:20 +0330
schrieb ali hagigat <address@hidden>:

> Thank you for the reply. When i was reading the section 4.13 of the
> manual, first i learned that if we use -M option,  compiler will
> generate some prerequisites for each #include of the C source file.
> But then the manual talks about having one makefile for each C source
> file. I am wondering what is the relationship of -M and having one
> makefile for every C file?
> -M is doing the job, it is creating some extra rules to show the
> dependency of C file to the files it has included, so what is the role
> of second technique?(having one makefile for each C source file) (This
> technique also adds new rules to our makefile?)
> That was my question......

FYI, the new GNU make based build system for does use
the -M switch to gcc to generate a dependency file for each object
file. Additionally it has a rule that concats all these
(object)-depfiles in one file per linked library. These files
(containing all object dependencies) are then #included by the main
makefile. Thereby a lot fewer files need to be opened by make (which
might slow down the build), but on the other hand the dependencies are
on the disc twice. But storage is cheap nowadays.

and followups for an overview and:
for the gory details ...

Best Regards,


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