Re: How to limit the assignment of variable from command line only to the current makefile?

[Paul Smith]

On Wed, 2011-07-13 at 11:06 -0500, Peng Yu wrote:
> The variable assigned in the parent makefile will be carried on to the
> child makefile.

No it won't.

> $ cat Makefile
> .PHONY: all
> 
> XX:=abc
> 
> $(info $(XX))
> 
> all:
>       $(MAKE) -C dir
> 
> $ cat dir/Makefile
> .PHONY: all
> 
> XX:=abc
> 
> $(info $(XX))
> 
> all:
> 
> $ make XX=100

You ran this with "XX=100" on the command line.  Command line settings
have the highest priority and always take precedence over values set in
the makefile.  They are also always passed down to sub-makes and so
override those as well; this allows things like "make CFLAGS=-O2" to
work properly.

As pointed out earlier, you can use "override" in a makefile if you want
to set a variable in a makefile overriding everything, even command line
settings--but I do not recommend this.

If you'd run "make" by itself you'd see that the assignment in the upper
level makefile does not take precedence over the one in the sub-make.

Similarly if you'd run "make XX=xyz" instead of "make XX=100" (so the
value of XX on the command line is not exactly the same setting as in
the top makefile) you'd see the output as "xyz" instead of "100" and it
would be clear what was happening.

-- 
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