Re: Clarification Needed on -C option

[Ajay Jain]

>> I use a make -C option in my top-level Makefile. This calls a leaf
>> Makefile to build, and checks CONFIG variable. If it not specified, it
>> assigns a default configuration to the same variable. The snippet is
>> as follows.
>>
>> ifeq ("$(CONFIG)","")
>>  $(info CONFIG Not Specified)
>>  CONFIG = $(DEFAULT_CONFIG)
>>  $(info Setting CONFIG to Default : $(CONFIG))
>> endif
>>
>> I see that this snipped executes twice in every invocation of Make.
>
> I don't see how that's possible (given the situation as you've described
> it).  Instead I think that the make is being invoked twice and that's
> why you see the variable being set twice.
>
> This could happen for at least two reasons: first, your parent makefile
> could be running the sub-make twice for some reason.  If you enable
> debug (or at least ensure that you're printing directory changes and
> don't have --no-print-directory set) you can see that.
>
> Second, you could be "include"ing another makefile which is also a
> target, and it's getting rebuilt then make is re-exec'ing itself.  Again
> the debug output should help determine if that's the case.  Look up
> "Remaking Makefiles" section in the manual for more info here.

You are correct ..
In my project, the parent Makefile is (and has always been) running
sub-make twice (and before you pointed this, I thought this was the
way). I see the following on screen:

make -C /xxx/dir1
make[1]: Entering directory '/xxx/dir1'
make[1]: Leaving directory '/xxx/dir1'
make[1]: Entering directory '/xxx/dir1'
CC src/test.c
make[1]: Leaving directory '/xxx/dir1'

I used to always think that since Make does two passes, we get the
Entering and Leaving prints twice. Is this an anomaly? What could be
the possible reasons?