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DSP FPGA design using open source / free software

From: Chipmuenk
Subject: DSP FPGA design using open source / free software
Date: Mon, 13 Feb 2012 03:28:42 -0800 (PST)

I'm starting a new thread as the original discussion ran under "Criticisms
agains Octave":

On Feb. 06 2012 CdeMills wrote:
>AFAIK, FPGA design tools are only available from FPGA vendors, there's no
open source version. 
>Wouldn't the maintenance of such setup be complicated ? I guess each new
release would introduce 
>some changes in the interfaces that we, with limited time and ressources,
would have to rush to 
>adapt ?

This is true, but only for the last step of generating the program code for
an FPGA (the "bit file"). With "last step" I mean the part of compiling the
VHDL or Verilog (in short: HDL) netlist and some project information (pin
mapping, constraint files etc.) into the bit file. This part of the software
is usually available for free, after all, the FPGA vendors want to sell
FPGAs, not software. Hence, the HDL netlist provides a standardized
interface for the FPGA design process, comparable perhaps to a SPICE netlist
in an analog circuit design. There are some options for obtaining an HDL

- Manual creation, using one a HDL-simulator of your choice. Problem: HDL
simulators are not well 
equipped for signal processing problems, i.e. stimulus creation (e.g.
modulated signals) and postprocessing capabilities (e.g. FFT) are very
meagre, only simple cases like sine sources or chirp pulses can be
implemented using behavioral VHDL. Solution: Use Octave to write stimulus
files which are read and processed by the HDL simulator, results are dumped
to a textfile that is processed by Octave. Additionally, filter design and
other high level tasks are also delegated to Octave. However, the actual HDL
code has to be written manually which not everyone is willing or capable of

- The latter problem can be solved by using FPGA vendors' block level,
"schematic entry" tools. My impression is that there is a lot of development
in this area, the blocks are already far more than simple parametrized VHDL
code. FFT and filter blocks can be created, these blocks are very efficient
as they have been taylored for the FPGA fabric by the vendors. Mostly, these
tools are also included in the free versions of the FPGA design suites. The
resulting HDL code can be used to the create the bit file directly or can be
exported to other flows.

- Several costly high-level synthesis tools utilizing Simulink are
available, either specific ones by the FPGA vendors or generic ones (usually
not very efficient). In any case, the Simulink block diagram is converted to
HDL code which is then compiled using the normal FPGA tools and flow.
Disadvantages: Expensive, highly "unfree" due to the double dependence on
Mathworks and the FPGA vendor. In appnotes this tool chain looks deceivingly
simply, but some nasty problems are lurking in the dark corners ...

- Recently, I discovered another option: Using Python and myHDL (both open
source), it seems to be possible to obtain a synthesizable HDL netlist: 

I have not tried this approach myself, but the tight integration of
algorithmic simulation and 
hardware design looks promising. 

Any experiences or ideas on your side?

Best regards,


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