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Re: [Help-smalltalk] [PATCH 01/15] opcode: Remove the copy of the binuti
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From: |
Paolo Bonzini |
|
Subject: |
Re: [Help-smalltalk] [PATCH 01/15] opcode: Remove the copy of the binutils code from the repository |
|
Date: |
Sun, 14 Apr 2013 15:37:56 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130311 Thunderbird/17.0.4 |
Il 08/04/2013 11:30, Holger Hans Peter Freyther ha scritto:
> From: Gwenael Casaccio <address@hidden>
>
> The disassemble function was never called, the opcode code is outdated,
> GNU lightning gained functionality to do the disassembly. For debugging
> implementing the GNU GDB JIT interface might be easier.
>
> 2013-01-21 Gwenael Casaccio <address@hidden>
>
> * main.c: Remove ENABLE_DISASSEMBLER support
> * opcode/dis-buf.c: Delete
> * opcode/disass.c: Delete
> * opcode/i386-dis.c: Delete
> * opcode/ppc-dis.c: Delete
> * opcode/ppc-opc.c: Delete
> * opcode/sparc-dis.c: Delete
> * opcode/sparc-opc.c: Delete
> ---
> ChangeLog | 11 +
> Makefile.am | 11 +-
> configure.ac | 11 +-
> main.c | 35 -
> opcode/Makefile.am | 8 -
> opcode/ansidecl.h | 17 -
> opcode/bfd.h | 185 ----
> opcode/dis-asm.h | 175 ----
> opcode/dis-buf.c | 70 --
> opcode/disass.c | 65 --
> opcode/i386-dis.c | 2031 -------------------------------------
> opcode/i386.h | 898 -----------------
> opcode/ppc-dis.c | 238 -----
> opcode/ppc-opc.c | 2830
> ----------------------------------------------------
> opcode/ppc.h | 248 -----
> opcode/sparc-dis.c | 868 ----------------
> opcode/sparc-opc.c | 1757 --------------------------------
> opcode/sparc.h | 220 ----
> opcode/sysdep.h | 3 -
> 19 files changed, 13 insertions(+), 9668 deletions(-)
> delete mode 100644 opcode/Makefile.am
> delete mode 100644 opcode/ansidecl.h
> delete mode 100644 opcode/bfd.h
> delete mode 100644 opcode/dis-asm.h
> delete mode 100644 opcode/dis-buf.c
> delete mode 100644 opcode/disass.c
> delete mode 100644 opcode/i386-dis.c
> delete mode 100644 opcode/i386.h
> delete mode 100644 opcode/ppc-dis.c
> delete mode 100644 opcode/ppc-opc.c
> delete mode 100644 opcode/ppc.h
> delete mode 100644 opcode/sparc-dis.c
> delete mode 100644 opcode/sparc-opc.c
> delete mode 100644 opcode/sparc.h
> delete mode 100644 opcode/sysdep.h
>
> diff --git a/ChangeLog b/ChangeLog
> index 5b8cf1b..2abc1c4 100644
> --- a/ChangeLog
> +++ b/ChangeLog
> @@ -1,3 +1,14 @@
> +2013-01-21 Gwenael Casaccio <address@hidden>
> +
> + * main.c: Remove ENABLE_DISASSEMBLER support
> + * opcode/dis-buf.c: Delete
> + * opcode/disass.c: Delete
> + * opcode/i386-dis.c: Delete
> + * opcode/ppc-dis.c: Delete
> + * opcode/ppc-opc.c: Delete
> + * opcode/sparc-dis.c: Delete
> + * opcode/sparc-opc.c: Delete
> +
> 2013-02-14 Holger Hans Peter Freyther <address@hidden>
>
> * kernel/StreamOps.st: Override the >>#species selector.
> diff --git a/Makefile.am b/Makefile.am
> index 732a72c..4641e83 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -22,13 +22,10 @@ ACLOCAL_AMFLAGS = -I build-aux
> PACKAGE=smalltalk
> gstdatadir=$(pkgdatadir)
>
> -DIST_SUBDIRS = lib-src snprintfv lightning opcode libgst \
> +DIST_SUBDIRS = lib-src snprintfv lightning libgst \
> . $(ALL_PACKAGES) tests doc
>
> SUBDIRS = lib-src lightning $(subdirs)
> -if ENABLE_DISASSEMBLER
> -SUBDIRS += opcode
> -endif
> SUBDIRS += libgst . $(BUILT_PACKAGES) doc tests
>
> # Running gst inside the build directory...
> @@ -115,12 +112,6 @@ gst_LDADD = libgst/libgst.la lib-src/library.la @ICON@
> gst_DEPENDENCIES = libgst/libgst.la lib-src/library.la @ICON@
> gst_LDFLAGS = -export-dynamic $(RELOC_LDFLAGS) $(LIBFFI_EXECUTABLE_LDFLAGS)
>
> -if ENABLE_DISASSEMBLER
> -gst_LDADD += opcode/libdisass.la
> -gst_DEPENDENCIES += opcode/libdisass.la
> -AM_CPPFLAGS += -I$(top_srcdir)/opcode
> -endif
> -
> # The single gst-tool executable is installed with multiple names, hence
> # we use noinst here.
> noinst_PROGRAMS = gst-tool
> diff --git a/configure.ac b/configure.ac
> index 29bf036..798a6a8 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -626,15 +626,6 @@ if test "$enable_jit" != no; then
> [Define to enable dynamic translation to machine code])
> fi
>
> -AC_ARG_ENABLE(disassembler,
> -[ --enable-disassembler include a disassembler in the gst executable], ,
> -enable_disassembler=no)
> -AM_CONDITIONAL(ENABLE_DISASSEMBLER, test "$enable_disassembler" != no)
> -if test "$enable_disassembler" != no; then
> - AC_DEFINE(ENABLE_DISASSEMBLER, 1,
> - [Define to include a disassembler in the gst executable])
> -fi
> -
> AC_ARG_ENABLE(dld,
> [ --disable-dld disable loading of external modules at runtime], ,
> enable_dld=yes)
> @@ -888,6 +879,6 @@ AC_CONFIG_FILES(Makefile)
>
> dnl VM makefiles
> AC_CONFIG_FILES(doc/Makefile lib-src/Makefile libgst/Makefile)
> -AC_CONFIG_FILES(opcode/Makefile lightning/Makefile tests/Makefile)
> +AC_CONFIG_FILES(lightning/Makefile tests/Makefile)
>
> AC_OUTPUT
> diff --git a/main.c b/main.c
> index 084c9ed..9c6bc60 100644
> --- a/main.c
> +++ b/main.c
> @@ -64,11 +64,6 @@
> #include <sys/stat.h>
> #include <errno.h>
>
> -#ifdef ENABLE_DISASSEMBLER
> -#define TRUE_FALSE_ALREADY_DEFINED
> -#include "dis-asm.h"
> -#endif
> -
> static const char help_text[] =
> "GNU Smalltalk usage:"
> "\n"
> @@ -424,33 +419,3 @@ main(int argc, const char **argv)
> exit (0);
> }
>
> -#ifdef ENABLE_DISASSEMBLER
> -void disassemble(stream, from, to)
> - FILE *stream;
> - char *from, *to;
> -{
> - disassemble_info info;
> - bfd_vma pc = (bfd_vma) from;
> - bfd_vma end = (bfd_vma) to;
> -
> - INIT_DISASSEMBLE_INFO(info, stream, fprintf);
> - info.buffer = NULL;
> - info.buffer_vma = 0;
> - info.buffer_length = end;
> -
> - while (pc < end) {
> - fprintf_vma(stream, pc);
> - putc('\t', stream);
> -#ifdef __i386__
> - pc += print_insn_i386(pc, &info);
> -#endif
> -#ifdef __ppc__
> - pc += print_insn_big_powerpc(pc, &info);
> -#endif
> -#ifdef __sparc__
> - pc += print_insn_sparc(pc, &info);
> -#endif
> - putc('\n', stream);
> - }
> -}
> -#endif
> diff --git a/opcode/Makefile.am b/opcode/Makefile.am
> deleted file mode 100644
> index d771581..0000000
> --- a/opcode/Makefile.am
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -noinst_LTLIBRARIES = libdisass.la
> -
> -AM_CPPFLAGS = -I$(top_srcdir)
> -
> -libdisass_la_SOURCES = dis-buf.c i386-dis.c ppc-dis.c ppc-opc.c sparc-dis.c \
> - sparc-opc.c disass.c
> -
> -noinst_HEADERS = ansidecl.h bfd.h dis-asm.h i386.h ppc.h sparc.h sysdep.h
> diff --git a/opcode/ansidecl.h b/opcode/ansidecl.h
> deleted file mode 100644
> index f0dd187..0000000
> --- a/opcode/ansidecl.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -#ifndef __ANSIDECL_H_SEEN
> -#define __ANSIDECL_H_SEEN
> -
> -#ifdef __STDC__
> -#define PARAMS(x) x
> -#ifndef PTR
> -typedef void *PTR;
> -#endif
> -#else
> -#define CONST const
> -#define PARAMS(x) ()
> -#ifndef PTR
> -typedef char *PTR;
> -#endif
> -#endif
> -
> -#endif
> diff --git a/opcode/bfd.h b/opcode/bfd.h
> deleted file mode 100644
> index 2f2669f..0000000
> --- a/opcode/bfd.h
> +++ /dev/null
> @@ -1,185 +0,0 @@
> -/* Main header file for the bfd library -- portable access to object files.
> - Copyright 1990, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
> - Contributed by Cygnus Support.
> -
> -This file is part of BFD, the Binary File Descriptor library.
> -(Simplified and modified for GNU lightning)
> -
> -This program is free software; you can redistribute it and/or modify
> -it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 2 of the License, or
> -(at your option) any later version.
> -
> -This program is distributed in the hope that it will be useful,
> -but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this program; if not, write to the Free Software
> -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -/* bfd.h -- The only header file required by users of the bfd library
> -
> -The bfd.h file is generated from bfd-in.h and various .c files; if you
> -change it, your changes will probably be lost.
> -
> -All the prototypes and definitions following the comment "THE FOLLOWING
> -IS EXTRACTED FROM THE SOURCE" are extracted from the source files for
> -BFD. If you change it, someone oneday will extract it from the source
> -again, and your changes will be lost. To save yourself from this bind,
> -change the definitions in the source in the bfd directory. Type "make
> -docs" and then "make headers" in that directory, and magically this file
> -will change to reflect your changes.
> -
> -If you don't have the tools to perform the extraction, then you are
> -safe from someone on your system trampling over your header files.
> -You should still maintain the equivalence between the source and this
> -file though; every change you make to the .c file should be reflected
> -here. */
> -
> -#ifndef __BFD_H_SEEN__
> -#define __BFD_H_SEEN__
> -
> -#include "ansidecl.h"
> -
> -#ifndef INLINE
> -#if __GNUC__ >= 2
> -#define INLINE __inline__
> -#else
> -#define INLINE
> -#endif
> -#endif
> -
> -/* To squelch erroneous compiler warnings ("illegal pointer
> - combination") from the SVR3 compiler, we would like to typedef
> - boolean to int (it doesn't like functions which return boolean.
> - Making sure they are never implicitly declared to return int
> - doesn't seem to help). But this file is not configured based on
> - the host. */
> -/* General rules: functions which are boolean return true on success
> - and false on failure (unless they're a predicate). -- bfd.doc */
> -/* I'm sure this is going to break something and someone is going to
> - force me to change it. */
> -/* typedef enum boolean {false, true} boolean; */
> -/* Yup, SVR4 has a "typedef enum boolean" in <sys/types.h> -fnf */
> -/* It gets worse if the host also defines a true/false enum... -sts */
> -/* And even worse if your compiler has built-in boolean types... -law */
> -#if defined (__GNUG__) && (__GNUC_MINOR__ > 5)
> -#define TRUE_FALSE_ALREADY_DEFINED
> -#endif
> -#ifdef MPW
> -/* Pre-emptive strike - get the file with the enum. */
> -#include <Types.h>
> -#define TRUE_FALSE_ALREADY_DEFINED
> -#endif /* MPW */
> -#ifndef TRUE_FALSE_ALREADY_DEFINED
> -typedef enum bfd_boolean {false, true} boolean;
> -#define BFD_TRUE_FALSE
> -#else
> -/* Use enum names that will appear nowhere else. */
> -typedef enum bfd_boolean {bfd_fffalse, bfd_tttrue} boolean;
> -#endif
> -
> -/* A pointer to a position in a file. */
> -/* FIXME: This should be using off_t from <sys/types.h>.
> - For now, try to avoid breaking stuff by not including <sys/types.h> here.
> - This will break on systems with 64-bit file offsets (e.g. 4.4BSD).
> - Probably the best long-term answer is to avoid using file_ptr AND off_t
> - in this header file, and to handle this in the BFD implementation
> - rather than in its interface. */
> -/* typedef off_t file_ptr; */
> -typedef long int file_ptr;
> -
> -/* Represent a target address. Also used as a generic unsigned type
> - which is guaranteed to be big enough to hold any arithmetic types
> - we need to deal with. */
> -typedef unsigned long bfd_vma;
> -
> -/* A generic signed type which is guaranteed to be big enough to hold any
> - arithmetic types we need to deal with. Can be assumed to be compatible
> - with bfd_vma in the same way that signed and unsigned ints are compatible
> - (as parameters, in assignment, etc). */
> -typedef long bfd_signed_vma;
> -
> -typedef unsigned long symvalue;
> -typedef unsigned long bfd_size_type;
> -
> -/* Print a bfd_vma x on stream s. */
> -#define fprintf_vma(s,x) fprintf(s, "%08lx", x)
> -#define sprintf_vma(s,x) sprintf(s, "%08lx", x)
> -#define printf_vma(x) fprintf_vma(stdout,x)
> -
> -typedef unsigned int flagword; /* 32 bits of flags */
> -typedef unsigned char bfd_byte;
> -
> -enum bfd_architecture
> -{
> - bfd_arch_unknown, /* File arch not known */
> - bfd_arch_obscure, /* Arch known, not one of these */
> - bfd_arch_m68k, /* Motorola 68xxx */
> - bfd_arch_vax, /* DEC Vax */
> - bfd_arch_i960, /* Intel 960 */
> - /* The order of the following is important.
> - lower number indicates a machine type that
> - only accepts a subset of the instructions
> - available to machines with higher numbers.
> - The exception is the "ca", which is
> - incompatible with all other machines except
> - "core". */
> -
> -#define bfd_mach_i960_core 1
> -#define bfd_mach_i960_ka_sa 2
> -#define bfd_mach_i960_kb_sb 3
> -#define bfd_mach_i960_mc 4
> -#define bfd_mach_i960_xa 5
> -#define bfd_mach_i960_ca 6
> -#define bfd_mach_i960_jx 7
> -#define bfd_mach_i960_hx 8
> -
> - bfd_arch_a29k, /* AMD 29000 */
> - bfd_arch_sparc, /* SPARC */
> -#define bfd_mach_sparc 1
> - /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
> -#define bfd_mach_sparc_v8plus 2
> -#define bfd_mach_sparc_v8plusa 3 /* with ultrasparc add'ns */
> -#define bfd_mach_sparc_v9 4
> -#define bfd_mach_sparc_v9a 5 /* with ultrasparc add'ns */
> - /* Nonzero if MACH has the v9 instruction set. */
> -#define bfd_mach_sparc_v9_p(mach) ((mach) != bfd_mach_sparc)
> - bfd_arch_mips, /* MIPS Rxxxx */
> - bfd_arch_i386, /* Intel 386 */
> - bfd_arch_we32k, /* AT&T WE32xxx */
> - bfd_arch_tahoe, /* CCI/Harris Tahoe */
> - bfd_arch_i860, /* Intel 860 */
> - bfd_arch_romp, /* IBM ROMP PC/RT */
> - bfd_arch_alliant, /* Alliant */
> - bfd_arch_convex, /* Convex */
> - bfd_arch_m88k, /* Motorola 88xxx */
> - bfd_arch_pyramid, /* Pyramid Technology */
> - bfd_arch_h8300, /* Hitachi H8/300 */
> -#define bfd_mach_h8300 1
> -#define bfd_mach_h8300h 2
> - bfd_arch_powerpc, /* PowerPC */
> - bfd_arch_rs6000, /* IBM RS/6000 */
> - bfd_arch_hppa, /* HP PA RISC */
> - bfd_arch_z8k, /* Zilog Z8000 */
> -#define bfd_mach_z8001 1
> -#define bfd_mach_z8002 2
> - bfd_arch_h8500, /* Hitachi H8/500 */
> - bfd_arch_sh, /* Hitachi SH */
> - bfd_arch_alpha, /* Dec Alpha */
> - bfd_arch_arm, /* Advanced Risc Machines ARM */
> - bfd_arch_ns32k, /* National Semiconductors ns32000 */
> - bfd_arch_w65, /* WDC 65816 */
> - bfd_arch_last
> - };
> -
> -enum bfd_endian { BFD_ENDIAN_UNKNOWN };
> -
> -typedef struct bfd bfd;
> -
> -#define bfd_getb32(x) *((int *)(x))
> -#define bfd_getl32(x) *((int *)(x))
> -
> -#endif
> diff --git a/opcode/dis-asm.h b/opcode/dis-asm.h
> deleted file mode 100644
> index d70bd51..0000000
> --- a/opcode/dis-asm.h
> +++ /dev/null
> @@ -1,175 +0,0 @@
> -/* Interface between the opcode library and its callers.
> - Written by Cygnus Support, 1993.
> -
> - The opcode library (libopcodes.a) provides instruction decoders for
> - a large variety of instruction sets, callable with an identical
> - interface, for making instruction-processing programs more independent
> - of the instruction set being processed. */
> -
> -#ifndef DIS_ASM_H
> -#define DIS_ASM_H
> -
> -#include <stdio.h>
> -#include "bfd.h"
> -
> -typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...));
> -
> -enum dis_insn_type {
> - dis_noninsn, /* Not a valid instruction */
> - dis_nonbranch, /* Not a branch instruction */
> - dis_branch, /* Unconditional branch */
> - dis_condbranch, /* Conditional branch */
> - dis_jsr, /* Jump to subroutine */
> - dis_condjsr, /* Conditional jump to subroutine */
> - dis_dref, /* Data reference instruction */
> - dis_dref2 /* Two data references in instruction */
> -};
> -
> -/* This struct is passed into the instruction decoding routine,
> - and is passed back out into each callback. The various fields are used
> - for conveying information from your main routine into your callbacks,
> - for passing information into the instruction decoders (such as the
> - addresses of the callback functions), or for passing information
> - back from the instruction decoders to their callers.
> -
> - It must be initialized before it is first passed; this can be done
> - by hand, or using one of the initialization macros below. */
> -
> -typedef struct disassemble_info {
> - fprintf_ftype fprintf_func;
> - FILE *stream;
> - PTR application_data;
> -
> - /* Target description. We could replace this with a pointer to the bfd,
> - but that would require one. There currently isn't any such requirement
> - so to avoid introducing one we record these explicitly. */
> - /* The bfd_arch value. */
> - enum bfd_architecture arch;
> - /* The bfd_mach value. */
> - unsigned long mach;
> - /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
> - enum bfd_endian endian;
> -
> - /* For use by the disassembler.
> - The top 16 bits are reserved for public use (and are documented here).
> - The bottom 16 bits are for the internal use of the disassembler. */
> - unsigned long flags;
> - PTR private_data;
> -
> - /* Function used to get bytes to disassemble. MEMADDR is the
> - address of the stuff to be disassembled, MYADDR is the address to
> - put the bytes in, and LENGTH is the number of bytes to read.
> - INFO is a pointer to this struct.
> - Returns an errno value or 0 for success. */
> - int (*read_memory_func)
> - PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
> - struct disassemble_info *info));
> -
> - /* Function which should be called if we get an error that we can't
> - recover from. STATUS is the errno value from read_memory_func and
> - MEMADDR is the address that we were trying to read. INFO is a
> - pointer to this struct. */
> - void (*memory_error_func)
> - PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info));
> -
> - /* Function called to print ADDR. */
> - void (*print_address_func)
> - PARAMS ((bfd_vma addr, struct disassemble_info *info));
> -
> - /* These are for buffer_read_memory. */
> - bfd_byte *buffer;
> - bfd_vma buffer_vma;
> - int buffer_length;
> -
> - /* Results from instruction decoders. Not all decoders yet support
> - this information. This info is set each time an instruction is
> - decoded, and is only valid for the last such instruction.
> -
> - To determine whether this decoder supports this information, set
> - insn_info_valid to 0, decode an instruction, then check it. */
> -
> - char insn_info_valid; /* Branch info has been set. */
> - char branch_delay_insns; /* How many sequential insn's will run before
> - a branch takes effect. (0 = normal) */
> - char data_size; /* Size of data reference in insn, in bytes */
> - enum dis_insn_type insn_type; /* Type of instruction */
> - bfd_vma target; /* Target address of branch or dref, if known;
> - zero if unknown. */
> - bfd_vma target2; /* Second target address for dref2 */
> -
> -} disassemble_info;
> -
> -
> -/* Standard disassemblers. Disassemble one instruction at the given
> - target address. Return number of bytes processed. */
> -typedef int (*disassembler_ftype)
> - PARAMS((bfd_vma, disassemble_info *));
> -
> -extern int print_insn_big_mips PARAMS ((bfd_vma,
> disassemble_info*));
> -extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_h8300 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_big_arm PARAMS ((bfd_vma,
> disassemble_info*));
> -extern int print_insn_little_arm PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_sparc64 PARAMS ((bfd_vma,
> disassemble_info*));
> -extern int print_insn_big_a29k PARAMS ((bfd_vma,
> disassemble_info*));
> -extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*));
> -extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*));
> -
> -/* Fetch the disassembler for a given BFD, if that support is available. */
> -extern disassembler_ftype disassembler PARAMS ((bfd *));
> -
> -
> -/* This block of definitions is for particular callers who read instructions
> - into a buffer before calling the instruction decoder. */
> -
> -/* Here is a function which callers may wish to use for read_memory_func.
> - It gets bytes from a buffer. */
> -extern int buffer_read_memory
> - PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *));
> -
> -/* This function goes with buffer_read_memory.
> - It prints a message using info->fprintf_func and info->stream. */
> -extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *));
> -
> -
> -/* Just print the address in hex. This is included for completeness even
> - though both GDB and objdump provide their own (to print symbolic
> - addresses). */
> -extern void generic_print_address
> - PARAMS ((bfd_vma, struct disassemble_info *));
> -
> -/* Macro to initialize a disassemble_info struct. This should be called
> - by all applications creating such a struct. */
> -#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
> - (INFO).fprintf_func = (FPRINTF_FUNC), \
> - (INFO).stream = (STREAM), \
> - (INFO).buffer = NULL, \
> - (INFO).buffer_vma = 0, \
> - (INFO).buffer_length = 0, \
> - (INFO).read_memory_func = buffer_read_memory, \
> - (INFO).memory_error_func = perror_memory, \
> - (INFO).print_address_func = generic_print_address, \
> - (INFO).arch = bfd_arch_unknown, \
> - (INFO).mach = 0, \
> - (INFO).endian = BFD_ENDIAN_UNKNOWN, \
> - (INFO).flags = 0, \
> - (INFO).insn_info_valid = 0
> -
> -#endif /* ! defined (DIS_ASM_H) */
> diff --git a/opcode/dis-buf.c b/opcode/dis-buf.c
> deleted file mode 100644
> index d04ddfd..0000000
> --- a/opcode/dis-buf.c
> +++ /dev/null
> @@ -1,70 +0,0 @@
> -/* Disassemble from a buffer, for GNU.
> - Copyright (C) 1993, 1994 Free Software Foundation, Inc.
> -
> -This program is free software; you can redistribute it and/or modify
> -it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 2 of the License, or
> -(at your option) any later version.
> -
> -This program is distributed in the hope that it will be useful,
> -but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this program; if not, write to the Free Software
> -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -#include "sysdep.h"
> -#include "dis-asm.h"
> -#include <errno.h>
> -
> -/* Get LENGTH bytes from info's buffer, at target address memaddr.
> - Transfer them to myaddr. */
> -int
> -buffer_read_memory (memaddr, myaddr, length, info)
> - bfd_vma memaddr;
> - bfd_byte *myaddr;
> - int length;
> - struct disassemble_info *info;
> -{
> - if (memaddr < info->buffer_vma
> - || memaddr + length > info->buffer_vma + info->buffer_length)
> - /* Out of bounds. Use EIO because GDB uses it. */
> - return EIO;
> - memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
> - return 0;
> -}
> -
> -/* Print an error message. We can assume that this is in response to
> - an error return from buffer_read_memory. */
> -void
> -perror_memory (status, memaddr, info)
> - int status;
> - bfd_vma memaddr;
> - struct disassemble_info *info;
> -{
> - if (status != EIO)
> - /* Can't happen. */
> - (*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
> - else
> - /* Actually, address between memaddr and memaddr + len was
> - out of bounds. */
> - (*info->fprintf_func) (info->stream,
> - "Address 0x%x is out of bounds.\n", memaddr);
> -}
> -
> -/* This could be in a separate file, to save miniscule amounts of space
> - in statically linked executables. */
> -
> -/* Just print the address is hex. This is included for completeness even
> - though both GDB and objdump provide their own (to print symbolic
> - addresses). */
> -
> -void
> -generic_print_address (addr, info)
> - bfd_vma addr;
> - struct disassemble_info *info;
> -{
> - (*info->fprintf_func) (info->stream, "0x%x", addr);
> -}
> diff --git a/opcode/disass.c b/opcode/disass.c
> deleted file mode 100644
> index 008a9d9..0000000
> --- a/opcode/disass.c
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -/******************************** -*- C -*- ****************************
> - *
> - * lightning disassembling support
> - *
> - ***********************************************************************/
> -
> -
> -/***********************************************************************
> - *
> - * Copyright 2000 Free Software Foundation, Inc.
> - * Written by Paolo Bonzini.
> - *
> - * This file is part of GNU lightning.
> - *
> - * GNU lightning is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU Lesser General Public License as published
> - * by the Free Software Foundation; either version 2.1, or (at your option)
> - * any later version.
> - *
> - * GNU lightning is distributed in the hope that it will be useful, but
> - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
> - * License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public License
> - * along with GNU lightning; see the file COPYING.LESSER; if not, write to
> the
> - * Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
> - * MA 02110-1301, USA.
> - *
> - ***********************************************************************/
> -
> -#include <stdio.h>
> -#include <stdlib.h>
> -#include "config.h"
> -#include "dis-asm.h"
> -
> -void disassemble(stream, from, to)
> - FILE *stream;
> - char *from, *to;
> -{
> - disassemble_info info;
> - bfd_vma pc = (bfd_vma) from;
> - bfd_vma end = (bfd_vma) to;
> -
> - INIT_DISASSEMBLE_INFO(info, stream, fprintf);
> - info.buffer = NULL;
> - info.buffer_vma = 0;
> - info.buffer_length = end;
> -
> - while (pc < end) {
> - fprintf_vma(stream, pc);
> - putc('\t', stream);
> -#ifdef LIGHTNING_I386
> - pc += print_insn_i386(pc, &info);
> -#endif
> -#ifdef LIGHTNING_PPC
> - pc += print_insn_big_powerpc(pc, &info);
> -#endif
> -#ifdef LIGHTNING_SPARC
> - pc += print_insn_sparc(pc, &info);
> -#endif
> - putc('\n', stream);
> - }
> -}
> -
> diff --git a/opcode/i386-dis.c b/opcode/i386-dis.c
> deleted file mode 100644
> index 1c2ebea..0000000
> --- a/opcode/i386-dis.c
> +++ /dev/null
> @@ -1,2031 +0,0 @@
> -/* Print i386 instructions for GDB, the GNU debugger.
> - Copyright (C) 1988, 89, 91, 93, 94, 95, 1996 Free Software Foundation,
> Inc.
> -
> -This file is part of GDB.
> -
> -This program is free software; you can redistribute it and/or modify
> -it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 2 of the License, or
> -(at your option) any later version.
> -
> -This program is distributed in the hope that it will be useful,
> -but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this program; if not, write to the Free Software
> -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -/*
> - * 80386 instruction printer by Pace Willisson (address@hidden)
> - * July 1988
> - * modified by John Hassey (address@hidden)
> - */
> -
> -/*
> - * The main tables describing the instructions is essentially a copy
> - * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
> - * Programmers Manual. Usually, there is a capital letter, followed
> - * by a small letter. The capital letter tell the addressing mode,
> - * and the small letter tells about the operand size. Refer to
> - * the Intel manual for details.
> - */
> -
> -#include "dis-asm.h"
> -#include "sysdep.h"
> -
> -#define MAXLEN 20
> -
> -#include <setjmp.h>
> -
> -struct dis_private
> -{
> - /* Points to first byte not fetched. */
> - bfd_byte *max_fetched;
> - bfd_byte the_buffer[MAXLEN];
> - bfd_vma insn_start;
> - jmp_buf bailout;
> -};
> -
> -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
> - to ADDR (exclusive) are valid. Returns 1 for success, longjmps
> - on error. */
> -#define FETCH_DATA(info, addr) \
> - ((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \
> - ? 1 : fetch_data ((info), (addr)))
> -
> -static int
> -fetch_data (info, addr)
> - struct disassemble_info *info;
> - bfd_byte *addr;
> -{
> - int status;
> - struct dis_private *priv = (struct dis_private *)info->private_data;
> - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
> -
> - status = (*info->read_memory_func) (start,
> - priv->max_fetched,
> - addr - priv->max_fetched,
> - info);
> - if (status != 0)
> - {
> - (*info->memory_error_func) (status, start, info);
> - longjmp (priv->bailout, 1);
> - }
> - else
> - priv->max_fetched = addr;
> - return 1;
> -}
> -
> -#define Eb OP_E, b_mode
> -#define indirEb OP_indirE, b_mode
> -#define Gb OP_G, b_mode
> -#define Ev OP_E, v_mode
> -#define indirEv OP_indirE, v_mode
> -#define Ew OP_E, w_mode
> -#define Ma OP_E, v_mode
> -#define M OP_E, 0
> -#define Mp OP_E, 0 /* ? */
> -#define Gv OP_G, v_mode
> -#define Gw OP_G, w_mode
> -#define Rw OP_rm, w_mode
> -#define Rd OP_rm, d_mode
> -#define Ib OP_I, b_mode
> -#define sIb OP_sI, b_mode /* sign extened byte */
> -#define Iv OP_I, v_mode
> -#define Iw OP_I, w_mode
> -#define Jb OP_J, b_mode
> -#define Jv OP_J, v_mode
> -#define ONE OP_ONE, 0
> -#define Cd OP_C, d_mode
> -#define Dd OP_D, d_mode
> -#define Td OP_T, d_mode
> -
> -#define eAX OP_REG, eAX_reg
> -#define eBX OP_REG, eBX_reg
> -#define eCX OP_REG, eCX_reg
> -#define eDX OP_REG, eDX_reg
> -#define eSP OP_REG, eSP_reg
> -#define eBP OP_REG, eBP_reg
> -#define eSI OP_REG, eSI_reg
> -#define eDI OP_REG, eDI_reg
> -#define AL OP_REG, al_reg
> -#define CL OP_REG, cl_reg
> -#define DL OP_REG, dl_reg
> -#define BL OP_REG, bl_reg
> -#define AH OP_REG, ah_reg
> -#define CH OP_REG, ch_reg
> -#define DH OP_REG, dh_reg
> -#define BH OP_REG, bh_reg
> -#define AX OP_REG, ax_reg
> -#define DX OP_REG, dx_reg
> -#define indirDX OP_REG, indir_dx_reg
> -
> -#define Sw OP_SEG, w_mode
> -#define Ap OP_DIR, lptr
> -#define Av OP_DIR, v_mode
> -#define Ob OP_OFF, b_mode
> -#define Ov OP_OFF, v_mode
> -#define Xb OP_DSSI, b_mode
> -#define Xv OP_DSSI, v_mode
> -#define Yb OP_ESDI, b_mode
> -#define Yv OP_ESDI, v_mode
> -
> -#define es OP_REG, es_reg
> -#define ss OP_REG, ss_reg
> -#define cs OP_REG, cs_reg
> -#define ds OP_REG, ds_reg
> -#define fs OP_REG, fs_reg
> -#define gs OP_REG, gs_reg
> -
> -int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
> -int OP_J(), OP_SEG();
> -int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
> -int OP_D(), OP_T(), OP_rm();
> -
> -static void dofloat (), putop (), append_prefix (), set_op ();
> -static int get16 (), get32 ();
> -
> -#define b_mode 1
> -#define v_mode 2
> -#define w_mode 3
> -#define d_mode 4
> -
> -#define es_reg 100
> -#define cs_reg 101
> -#define ss_reg 102
> -#define ds_reg 103
> -#define fs_reg 104
> -#define gs_reg 105
> -#define eAX_reg 107
> -#define eCX_reg 108
> -#define eDX_reg 109
> -#define eBX_reg 110
> -#define eSP_reg 111
> -#define eBP_reg 112
> -#define eSI_reg 113
> -#define eDI_reg 114
> -
> -#define lptr 115
> -
> -#define al_reg 116
> -#define cl_reg 117
> -#define dl_reg 118
> -#define bl_reg 119
> -#define ah_reg 120
> -#define ch_reg 121
> -#define dh_reg 122
> -#define bh_reg 123
> -
> -#define ax_reg 124
> -#define cx_reg 125
> -#define dx_reg 126
> -#define bx_reg 127
> -#define sp_reg 128
> -#define bp_reg 129
> -#define si_reg 130
> -#define di_reg 131
> -
> -#define indir_dx_reg 150
> -
> -#define GRP1b NULL, NULL, 0
> -#define GRP1S NULL, NULL, 1
> -#define GRP1Ss NULL, NULL, 2
> -#define GRP2b NULL, NULL, 3
> -#define GRP2S NULL, NULL, 4
> -#define GRP2b_one NULL, NULL, 5
> -#define GRP2S_one NULL, NULL, 6
> -#define GRP2b_cl NULL, NULL, 7
> -#define GRP2S_cl NULL, NULL, 8
> -#define GRP3b NULL, NULL, 9
> -#define GRP3S NULL, NULL, 10
> -#define GRP4 NULL, NULL, 11
> -#define GRP5 NULL, NULL, 12
> -#define GRP6 NULL, NULL, 13
> -#define GRP7 NULL, NULL, 14
> -#define GRP8 NULL, NULL, 15
> -#define GRP9 NULL, NULL, 16
> -
> -#define FLOATCODE 50
> -#define FLOAT NULL, NULL, FLOATCODE
> -
> -struct dis386 {
> - char *name;
> - int (*op1)();
> - int bytemode1;
> - int (*op2)();
> - int bytemode2;
> - int (*op3)();
> - int bytemode3;
> -};
> -
> -struct dis386 dis386[] = {
> - /* 00 */
> - { "addb", Eb, Gb },
> - { "addS", Ev, Gv },
> - { "addb", Gb, Eb },
> - { "addS", Gv, Ev },
> - { "addb", AL, Ib },
> - { "addS", eAX, Iv },
> - { "pushl", es },
> - { "popl", es },
> - /* 08 */
> - { "orb", Eb, Gb },
> - { "orS", Ev, Gv },
> - { "orb", Gb, Eb },
> - { "orS", Gv, Ev },
> - { "orb", AL, Ib },
> - { "orS", eAX, Iv },
> - { "pushl", cs },
> - { "(bad)" }, /* 0x0f extended opcode escape */
> - /* 10 */
> - { "adcb", Eb, Gb },
> - { "adcS", Ev, Gv },
> - { "adcb", Gb, Eb },
> - { "adcS", Gv, Ev },
> - { "adcb", AL, Ib },
> - { "adcS", eAX, Iv },
> - { "pushl", ss },
> - { "popl", ss },
> - /* 18 */
> - { "sbbb", Eb, Gb },
> - { "sbbS", Ev, Gv },
> - { "sbbb", Gb, Eb },
> - { "sbbS", Gv, Ev },
> - { "sbbb", AL, Ib },
> - { "sbbS", eAX, Iv },
> - { "pushl", ds },
> - { "popl", ds },
> - /* 20 */
> - { "andb", Eb, Gb },
> - { "andS", Ev, Gv },
> - { "andb", Gb, Eb },
> - { "andS", Gv, Ev },
> - { "andb", AL, Ib },
> - { "andS", eAX, Iv },
> - { "(bad)" }, /* SEG ES prefix */
> - { "daa" },
> - /* 28 */
> - { "subb", Eb, Gb },
> - { "subS", Ev, Gv },
> - { "subb", Gb, Eb },
> - { "subS", Gv, Ev },
> - { "subb", AL, Ib },
> - { "subS", eAX, Iv },
> - { "(bad)" }, /* SEG CS prefix */
> - { "das" },
> - /* 30 */
> - { "xorb", Eb, Gb },
> - { "xorS", Ev, Gv },
> - { "xorb", Gb, Eb },
> - { "xorS", Gv, Ev },
> - { "xorb", AL, Ib },
> - { "xorS", eAX, Iv },
> - { "(bad)" }, /* SEG SS prefix */
> - { "aaa" },
> - /* 38 */
> - { "cmpb", Eb, Gb },
> - { "cmpS", Ev, Gv },
> - { "cmpb", Gb, Eb },
> - { "cmpS", Gv, Ev },
> - { "cmpb", AL, Ib },
> - { "cmpS", eAX, Iv },
> - { "(bad)" }, /* SEG DS prefix */
> - { "aas" },
> - /* 40 */
> - { "incS", eAX },
> - { "incS", eCX },
> - { "incS", eDX },
> - { "incS", eBX },
> - { "incS", eSP },
> - { "incS", eBP },
> - { "incS", eSI },
> - { "incS", eDI },
> - /* 48 */
> - { "decS", eAX },
> - { "decS", eCX },
> - { "decS", eDX },
> - { "decS", eBX },
> - { "decS", eSP },
> - { "decS", eBP },
> - { "decS", eSI },
> - { "decS", eDI },
> - /* 50 */
> - { "pushS", eAX },
> - { "pushS", eCX },
> - { "pushS", eDX },
> - { "pushS", eBX },
> - { "pushS", eSP },
> - { "pushS", eBP },
> - { "pushS", eSI },
> - { "pushS", eDI },
> - /* 58 */
> - { "popS", eAX },
> - { "popS", eCX },
> - { "popS", eDX },
> - { "popS", eBX },
> - { "popS", eSP },
> - { "popS", eBP },
> - { "popS", eSI },
> - { "popS", eDI },
> - /* 60 */
> - { "pusha" },
> - { "popa" },
> - { "boundS", Gv, Ma },
> - { "arpl", Ew, Gw },
> - { "(bad)" }, /* seg fs */
> - { "(bad)" }, /* seg gs */
> - { "(bad)" }, /* op size prefix */
> - { "(bad)" }, /* adr size prefix */
> - /* 68 */
> - { "pushS", Iv }, /* 386 book wrong */
> - { "imulS", Gv, Ev, Iv },
> - { "pushl", sIb }, /* push of byte really pushes 4 bytes */
> - { "imulS", Gv, Ev, Ib },
> - { "insb", Yb, indirDX },
> - { "insS", Yv, indirDX },
> - { "outsb", indirDX, Xb },
> - { "outsS", indirDX, Xv },
> - /* 70 */
> - { "jo", Jb },
> - { "jno", Jb },
> - { "jb", Jb },
> - { "jae", Jb },
> - { "je", Jb },
> - { "jne", Jb },
> - { "jbe", Jb },
> - { "ja", Jb },
> - /* 78 */
> - { "js", Jb },
> - { "jns", Jb },
> - { "jp", Jb },
> - { "jnp", Jb },
> - { "jl", Jb },
> - { "jnl", Jb },
> - { "jle", Jb },
> - { "jg", Jb },
> - /* 80 */
> - { GRP1b },
> - { GRP1S },
> - { "(bad)" },
> - { GRP1Ss },
> - { "testb", Eb, Gb },
> - { "testS", Ev, Gv },
> - { "xchgb", Eb, Gb },
> - { "xchgS", Ev, Gv },
> - /* 88 */
> - { "movb", Eb, Gb },
> - { "movS", Ev, Gv },
> - { "movb", Gb, Eb },
> - { "movS", Gv, Ev },
> - { "movw", Ew, Sw },
> - { "leaS", Gv, M },
> - { "movw", Sw, Ew },
> - { "popS", Ev },
> - /* 90 */
> - { "nop" },
> - { "xchgS", eCX, eAX },
> - { "xchgS", eDX, eAX },
> - { "xchgS", eBX, eAX },
> - { "xchgS", eSP, eAX },
> - { "xchgS", eBP, eAX },
> - { "xchgS", eSI, eAX },
> - { "xchgS", eDI, eAX },
> - /* 98 */
> - { "cwtl" },
> - { "cltd" },
> - { "lcall", Ap },
> - { "(bad)" }, /* fwait */
> - { "pushf" },
> - { "popf" },
> - { "sahf" },
> - { "lahf" },
> - /* a0 */
> - { "movb", AL, Ob },
> - { "movS", eAX, Ov },
> - { "movb", Ob, AL },
> - { "movS", Ov, eAX },
> - { "movsb", Yb, Xb },
> - { "movsS", Yv, Xv },
> - { "cmpsb", Yb, Xb },
> - { "cmpsS", Yv, Xv },
> - /* a8 */
> - { "testb", AL, Ib },
> - { "testS", eAX, Iv },
> - { "stosb", Yb, AL },
> - { "stosS", Yv, eAX },
> - { "lodsb", AL, Xb },
> - { "lodsS", eAX, Xv },
> - { "scasb", AL, Yb },
> - { "scasS", eAX, Yv },
> - /* b0 */
> - { "movb", AL, Ib },
> - { "movb", CL, Ib },
> - { "movb", DL, Ib },
> - { "movb", BL, Ib },
> - { "movb", AH, Ib },
> - { "movb", CH, Ib },
> - { "movb", DH, Ib },
> - { "movb", BH, Ib },
> - /* b8 */
> - { "movS", eAX, Iv },
> - { "movS", eCX, Iv },
> - { "movS", eDX, Iv },
> - { "movS", eBX, Iv },
> - { "movS", eSP, Iv },
> - { "movS", eBP, Iv },
> - { "movS", eSI, Iv },
> - { "movS", eDI, Iv },
> - /* c0 */
> - { GRP2b },
> - { GRP2S },
> - { "ret", Iw },
> - { "ret" },
> - { "lesS", Gv, Mp },
> - { "ldsS", Gv, Mp },
> - { "movb", Eb, Ib },
> - { "movS", Ev, Iv },
> - /* c8 */
> - { "enter", Iw, Ib },
> - { "leave" },
> - { "lret", Iw },
> - { "lret" },
> - { "int3" },
> - { "int", Ib },
> - { "into" },
> - { "iret" },
> - /* d0 */
> - { GRP2b_one },
> - { GRP2S_one },
> - { GRP2b_cl },
> - { GRP2S_cl },
> - { "aam", Ib },
> - { "aad", Ib },
> - { "(bad)" },
> - { "xlat" },
> - /* d8 */
> - { FLOAT },
> - { FLOAT },
> - { FLOAT },
> - { FLOAT },
> - { FLOAT },
> - { FLOAT },
> - { FLOAT },
> - { FLOAT },
> - /* e0 */
> - { "loopne", Jb },
> - { "loope", Jb },
> - { "loop", Jb },
> - { "jCcxz", Jb },
> - { "inb", AL, Ib },
> - { "inS", eAX, Ib },
> - { "outb", Ib, AL },
> - { "outS", Ib, eAX },
> - /* e8 */
> - { "call", Av },
> - { "jmp", Jv },
> - { "ljmp", Ap },
> - { "jmp", Jb },
> - { "inb", AL, indirDX },
> - { "inS", eAX, indirDX },
> - { "outb", indirDX, AL },
> - { "outS", indirDX, eAX },
> - /* f0 */
> - { "(bad)" }, /* lock prefix */
> - { "(bad)" },
> - { "(bad)" }, /* repne */
> - { "(bad)" }, /* repz */
> - { "hlt" },
> - { "cmc" },
> - { GRP3b },
> - { GRP3S },
> - /* f8 */
> - { "clc" },
> - { "stc" },
> - { "cli" },
> - { "sti" },
> - { "cld" },
> - { "std" },
> - { GRP4 },
> - { GRP5 },
> -};
> -
> -struct dis386 dis386_twobyte[] = {
> - /* 00 */
> - { GRP6 },
> - { GRP7 },
> - { "larS", Gv, Ew },
> - { "lslS", Gv, Ew },
> - { "(bad)" },
> - { "(bad)" },
> - { "clts" },
> - { "(bad)" },
> - /* 08 */
> - { "invd" },
> - { "wbinvd" },
> - { "(bad)" }, { "ud2a" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 10 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 18 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 20 */
> - /* these are all backward in appendix A of the intel book */
> - { "movl", Rd, Cd },
> - { "movl", Rd, Dd },
> - { "movl", Cd, Rd },
> - { "movl", Dd, Rd },
> - { "movl", Rd, Td },
> - { "(bad)" },
> - { "movl", Td, Rd },
> - { "(bad)" },
> - /* 28 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 30 */
> - { "wrmsr" }, { "rdtsc" }, { "rdmsr" }, { "rdpmc" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 38 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 40 */
> - { "cmovo", Gv,Ev }, { "cmovno", Gv,Ev }, { "cmovb", Gv,Ev }, { "cmovae",
> Gv,Ev },
> - { "cmove", Gv,Ev }, { "cmovne", Gv,Ev }, { "cmovbe", Gv,Ev }, { "cmova",
> Gv,Ev },
> - /* 48 */
> - { "cmovs", Gv,Ev }, { "cmovns", Gv,Ev }, { "cmovp", Gv,Ev }, { "cmovnp",
> Gv,Ev },
> - { "cmovl", Gv,Ev }, { "cmovge", Gv,Ev }, { "cmovle", Gv,Ev }, { "cmovg",
> Gv,Ev },
> - /* 50 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 58 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 60 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 68 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 70 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 78 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* 80 */
> - { "jo", Jv },
> - { "jno", Jv },
> - { "jb", Jv },
> - { "jae", Jv },
> - { "je", Jv },
> - { "jne", Jv },
> - { "jbe", Jv },
> - { "ja", Jv },
> - /* 88 */
> - { "js", Jv },
> - { "jns", Jv },
> - { "jp", Jv },
> - { "jnp", Jv },
> - { "jl", Jv },
> - { "jge", Jv },
> - { "jle", Jv },
> - { "jg", Jv },
> - /* 90 */
> - { "seto", Eb },
> - { "setno", Eb },
> - { "setb", Eb },
> - { "setae", Eb },
> - { "sete", Eb },
> - { "setne", Eb },
> - { "setbe", Eb },
> - { "seta", Eb },
> - /* 98 */
> - { "sets", Eb },
> - { "setns", Eb },
> - { "setp", Eb },
> - { "setnp", Eb },
> - { "setl", Eb },
> - { "setge", Eb },
> - { "setle", Eb },
> - { "setg", Eb },
> - /* a0 */
> - { "pushl", fs },
> - { "popl", fs },
> - { "cpuid" },
> - { "btS", Ev, Gv },
> - { "shldS", Ev, Gv, Ib },
> - { "shldS", Ev, Gv, CL },
> - { "(bad)" },
> - { "(bad)" },
> - /* a8 */
> - { "pushl", gs },
> - { "popl", gs },
> - { "rsm" },
> - { "btsS", Ev, Gv },
> - { "shrdS", Ev, Gv, Ib },
> - { "shrdS", Ev, Gv, CL },
> - { "(bad)" },
> - { "imulS", Gv, Ev },
> - /* b0 */
> - { "cmpxchgb", Eb, Gb },
> - { "cmpxchgS", Ev, Gv },
> - { "lssS", Gv, Mp }, /* 386 lists only Mp */
> - { "btrS", Ev, Gv },
> - { "lfsS", Gv, Mp }, /* 386 lists only Mp */
> - { "lgsS", Gv, Mp }, /* 386 lists only Mp */
> - { "movzbS", Gv, Eb },
> - { "movzwS", Gv, Ew },
> - /* b8 */
> - { "ud2b" },
> - { "(bad)" },
> - { GRP8 },
> - { "btcS", Ev, Gv },
> - { "bsfS", Gv, Ev },
> - { "bsrS", Gv, Ev },
> - { "movsbS", Gv, Eb },
> - { "movswS", Gv, Ew },
> - /* c0 */
> - { "xaddb", Eb, Gb },
> - { "xaddS", Ev, Gv },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { GRP9 },
> - /* c8 */
> - { "bswap", eAX },
> - { "bswap", eCX },
> - { "bswap", eDX },
> - { "bswap", eBX },
> - { "bswap", eSP },
> - { "bswap", eBP },
> - { "bswap", eSI },
> - { "bswap", eDI },
> - /* d0 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* d8 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* e0 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* e8 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* f0 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - /* f8 */
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
> -};
> -
> -static const unsigned char onebyte_has_modrm[256] = {
> - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
> - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
> - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
> - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
> - 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1
> -};
> -
> -static const unsigned char twobyte_has_modrm[256] = {
> - 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
> - 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1,
> - 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1,
> - 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
> - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
> -};
> -
> -static char obuf[100];
> -static char *obufp;
> -static char scratchbuf[100];
> -static unsigned char *start_codep;
> -static unsigned char *codep;
> -static disassemble_info *the_info;
> -static int mod;
> -static int rm;
> -static int reg;
> -static void oappend ();
> -
> -static char *names32[]={
> - "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
> -};
> -static char *names16[] = {
> - "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
> -};
> -static char *names8[] = {
> - "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
> -};
> -static char *names_seg[] = {
> - "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
> -};
> -static char *index16[] = {
> - "bx+si","bx+di","bp+si","bp+di","si","di","bp","bx"
> -};
> -
> -struct dis386 grps[][8] = {
> - /* GRP1b */
> - {
> - { "addb", Eb, Ib },
> - { "orb", Eb, Ib },
> - { "adcb", Eb, Ib },
> - { "sbbb", Eb, Ib },
> - { "andb", Eb, Ib },
> - { "subb", Eb, Ib },
> - { "xorb", Eb, Ib },
> - { "cmpb", Eb, Ib }
> - },
> - /* GRP1S */
> - {
> - { "addS", Ev, Iv },
> - { "orS", Ev, Iv },
> - { "adcS", Ev, Iv },
> - { "sbbS", Ev, Iv },
> - { "andS", Ev, Iv },
> - { "subS", Ev, Iv },
> - { "xorS", Ev, Iv },
> - { "cmpS", Ev, Iv }
> - },
> - /* GRP1Ss */
> - {
> - { "addS", Ev, sIb },
> - { "orS", Ev, sIb },
> - { "adcS", Ev, sIb },
> - { "sbbS", Ev, sIb },
> - { "andS", Ev, sIb },
> - { "subS", Ev, sIb },
> - { "xorS", Ev, sIb },
> - { "cmpS", Ev, sIb }
> - },
> - /* GRP2b */
> - {
> - { "rolb", Eb, Ib },
> - { "rorb", Eb, Ib },
> - { "rclb", Eb, Ib },
> - { "rcrb", Eb, Ib },
> - { "shlb", Eb, Ib },
> - { "shrb", Eb, Ib },
> - { "(bad)" },
> - { "sarb", Eb, Ib },
> - },
> - /* GRP2S */
> - {
> - { "rolS", Ev, Ib },
> - { "rorS", Ev, Ib },
> - { "rclS", Ev, Ib },
> - { "rcrS", Ev, Ib },
> - { "shlS", Ev, Ib },
> - { "shrS", Ev, Ib },
> - { "(bad)" },
> - { "sarS", Ev, Ib },
> - },
> - /* GRP2b_one */
> - {
> - { "rolb", Eb },
> - { "rorb", Eb },
> - { "rclb", Eb },
> - { "rcrb", Eb },
> - { "shlb", Eb },
> - { "shrb", Eb },
> - { "(bad)" },
> - { "sarb", Eb },
> - },
> - /* GRP2S_one */
> - {
> - { "rolS", Ev },
> - { "rorS", Ev },
> - { "rclS", Ev },
> - { "rcrS", Ev },
> - { "shlS", Ev },
> - { "shrS", Ev },
> - { "(bad)" },
> - { "sarS", Ev },
> - },
> - /* GRP2b_cl */
> - {
> - { "rolb", Eb, CL },
> - { "rorb", Eb, CL },
> - { "rclb", Eb, CL },
> - { "rcrb", Eb, CL },
> - { "shlb", Eb, CL },
> - { "shrb", Eb, CL },
> - { "(bad)" },
> - { "sarb", Eb, CL },
> - },
> - /* GRP2S_cl */
> - {
> - { "rolS", Ev, CL },
> - { "rorS", Ev, CL },
> - { "rclS", Ev, CL },
> - { "rcrS", Ev, CL },
> - { "shlS", Ev, CL },
> - { "shrS", Ev, CL },
> - { "(bad)" },
> - { "sarS", Ev, CL }
> - },
> - /* GRP3b */
> - {
> - { "testb", Eb, Ib },
> - { "(bad)", Eb },
> - { "notb", Eb },
> - { "negb", Eb },
> - { "mulb", AL, Eb },
> - { "imulb", AL, Eb },
> - { "divb", AL, Eb },
> - { "idivb", AL, Eb }
> - },
> - /* GRP3S */
> - {
> - { "testS", Ev, Iv },
> - { "(bad)" },
> - { "notS", Ev },
> - { "negS", Ev },
> - { "mulS", eAX, Ev },
> - { "imulS", eAX, Ev },
> - { "divS", eAX, Ev },
> - { "idivS", eAX, Ev },
> - },
> - /* GRP4 */
> - {
> - { "incb", Eb },
> - { "decb", Eb },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - },
> - /* GRP5 */
> - {
> - { "incS", Ev },
> - { "decS", Ev },
> - { "call", indirEv },
> - { "lcall", indirEv },
> - { "jmp", indirEv },
> - { "ljmp", indirEv },
> - { "pushS", Ev },
> - { "(bad)" },
> - },
> - /* GRP6 */
> - {
> - { "sldt", Ew },
> - { "str", Ew },
> - { "lldt", Ew },
> - { "ltr", Ew },
> - { "verr", Ew },
> - { "verw", Ew },
> - { "(bad)" },
> - { "(bad)" }
> - },
> - /* GRP7 */
> - {
> - { "sgdt", Ew },
> - { "sidt", Ew },
> - { "lgdt", Ew },
> - { "lidt", Ew },
> - { "smsw", Ew },
> - { "(bad)" },
> - { "lmsw", Ew },
> - { "invlpg", Ew },
> - },
> - /* GRP8 */
> - {
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "btS", Ev, Ib },
> - { "btsS", Ev, Ib },
> - { "btrS", Ev, Ib },
> - { "btcS", Ev, Ib },
> - },
> - /* GRP9 */
> - {
> - { "(bad)" },
> - { "cmpxchg8b", Ev },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - }
> -};
> -
> -#define PREFIX_REPZ 1
> -#define PREFIX_REPNZ 2
> -#define PREFIX_LOCK 4
> -#define PREFIX_CS 8
> -#define PREFIX_SS 0x10
> -#define PREFIX_DS 0x20
> -#define PREFIX_ES 0x40
> -#define PREFIX_FS 0x80
> -#define PREFIX_GS 0x100
> -#define PREFIX_DATA 0x200
> -#define PREFIX_ADR 0x400
> -#define PREFIX_FWAIT 0x800
> -
> -static int prefixes;
> -
> -static void
> -ckprefix ()
> -{
> - prefixes = 0;
> - while (1)
> - {
> - FETCH_DATA (the_info, codep + 1);
> - switch (*codep)
> - {
> - case 0xf3:
> - prefixes |= PREFIX_REPZ;
> - break;
> - case 0xf2:
> - prefixes |= PREFIX_REPNZ;
> - break;
> - case 0xf0:
> - prefixes |= PREFIX_LOCK;
> - break;
> - case 0x2e:
> - prefixes |= PREFIX_CS;
> - break;
> - case 0x36:
> - prefixes |= PREFIX_SS;
> - break;
> - case 0x3e:
> - prefixes |= PREFIX_DS;
> - break;
> - case 0x26:
> - prefixes |= PREFIX_ES;
> - break;
> - case 0x64:
> - prefixes |= PREFIX_FS;
> - break;
> - case 0x65:
> - prefixes |= PREFIX_GS;
> - break;
> - case 0x66:
> - prefixes |= PREFIX_DATA;
> - break;
> - case 0x67:
> - prefixes |= PREFIX_ADR;
> - break;
> - case 0x9b:
> - prefixes |= PREFIX_FWAIT;
> - break;
> - default:
> - return;
> - }
> - codep++;
> - }
> -}
> -
> -static int dflag;
> -static int aflag;
> -
> -static char op1out[100], op2out[100], op3out[100];
> -static int op_address[3], op_ad, op_index[3];
> -static int start_pc;
> -
> -
> -/*
> - * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
> - * (see topic "Redundant prefixes" in the "Differences from 8086"
> - * section of the "Virtual 8086 Mode" chapter.)
> - * 'pc' should be the address of this instruction, it will
> - * be used to print the target address if this is a relative jump or call
> - * The function returns the length of this instruction in bytes.
> - */
> -
> -int
> -print_insn_i386 (pc, info)
> - bfd_vma pc;
> - disassemble_info *info;
> -{
> - struct dis386 *dp;
> - int i;
> - int enter_instruction;
> - char *first, *second, *third;
> - int needcomma;
> - unsigned char need_modrm;
> -
> - struct dis_private priv;
> - bfd_byte *inbuf = priv.the_buffer;
> -
> - info->private_data = (PTR) &priv;
> - priv.max_fetched = priv.the_buffer;
> - priv.insn_start = pc;
> - if (setjmp (priv.bailout) != 0)
> - /* Error return. */
> - return -1;
> -
> - obuf[0] = 0;
> - op1out[0] = 0;
> - op2out[0] = 0;
> - op3out[0] = 0;
> -
> - op_index[0] = op_index[1] = op_index[2] = -1;
> -
> - the_info = info;
> - start_pc = pc;
> - start_codep = inbuf;
> - codep = inbuf;
> -
> - ckprefix ();
> -
> - FETCH_DATA (info, codep + 1);
> - if (*codep == 0xc8)
> - enter_instruction = 1;
> - else
> - enter_instruction = 0;
> -
> - obufp = obuf;
> -
> - if (prefixes & PREFIX_REPZ)
> - oappend ("repz ");
> - if (prefixes & PREFIX_REPNZ)
> - oappend ("repnz ");
> - if (prefixes & PREFIX_LOCK)
> - oappend ("lock ");
> -
> - if ((prefixes & PREFIX_FWAIT)
> - && ((*codep < 0xd8) || (*codep > 0xdf)))
> - {
> - /* fwait not followed by floating point instruction */
> - (*info->fprintf_func) (info->stream, "fwait");
> - return (1);
> - }
> -
> - /* these would be initialized to 0 if disassembling for 8086 or 286 */
> - dflag = 1;
> - aflag = 1;
> -
> - if (prefixes & PREFIX_DATA)
> - dflag ^= 1;
> -
> - if (prefixes & PREFIX_ADR)
> - {
> - aflag ^= 1;
> - oappend ("addr16 ");
> - }
> -
> - if (*codep == 0x0f)
> - {
> - FETCH_DATA (info, codep + 2);
> - dp = &dis386_twobyte[*++codep];
> - need_modrm = twobyte_has_modrm[*codep];
> - }
> - else
> - {
> - dp = &dis386[*codep];
> - need_modrm = onebyte_has_modrm[*codep];
> - }
> - codep++;
> -
> - if (need_modrm)
> - {
> - FETCH_DATA (info, codep + 1);
> - mod = (*codep >> 6) & 3;
> - reg = (*codep >> 3) & 7;
> - rm = *codep & 7;
> - }
> -
> - if (dp->name == NULL && dp->bytemode1 == FLOATCODE)
> - {
> - dofloat ();
> - }
> - else
> - {
> - if (dp->name == NULL)
> - dp = &grps[dp->bytemode1][reg];
> -
> - putop (dp->name);
> -
> - obufp = op1out;
> - op_ad = 2;
> - if (dp->op1)
> - (*dp->op1)(dp->bytemode1);
> -
> - obufp = op2out;
> - op_ad = 1;
> - if (dp->op2)
> - (*dp->op2)(dp->bytemode2);
> -
> - obufp = op3out;
> - op_ad = 0;
> - if (dp->op3)
> - (*dp->op3)(dp->bytemode3);
> - }
> -
> - obufp = obuf + strlen (obuf);
> - for (i = strlen (obuf); i < 6; i++)
> - oappend (" ");
> - oappend (" ");
> - (*info->fprintf_func) (info->stream, "%s", obuf);
> -
> - /* enter instruction is printed with operands in the
> - * same order as the intel book; everything else
> - * is printed in reverse order
> - */
> - if (enter_instruction)
> - {
> - first = op1out;
> - second = op2out;
> - third = op3out;
> - op_ad = op_index[0];
> - op_index[0] = op_index[2];
> - op_index[2] = op_ad;
> - }
> - else
> - {
> - first = op3out;
> - second = op2out;
> - third = op1out;
> - }
> - needcomma = 0;
> - if (*first)
> - {
> - if (op_index[0] != -1)
> - (*info->print_address_func) (op_address[op_index[0]], info);
> - else
> - (*info->fprintf_func) (info->stream, "%s", first);
> - needcomma = 1;
> - }
> - if (*second)
> - {
> - if (needcomma)
> - (*info->fprintf_func) (info->stream, ",");
> - if (op_index[1] != -1)
> - (*info->print_address_func) (op_address[op_index[1]], info);
> - else
> - (*info->fprintf_func) (info->stream, "%s", second);
> - needcomma = 1;
> - }
> - if (*third)
> - {
> - if (needcomma)
> - (*info->fprintf_func) (info->stream, ",");
> - if (op_index[2] != -1)
> - (*info->print_address_func) (op_address[op_index[2]], info);
> - else
> - (*info->fprintf_func) (info->stream, "%s", third);
> - }
> - return (codep - inbuf);
> -}
> -
> -char *float_mem[] = {
> - /* d8 */
> - "fadds",
> - "fmuls",
> - "fcoms",
> - "fcomps",
> - "fsubs",
> - "fsubrs",
> - "fdivs",
> - "fdivrs",
> - /* d9 */
> - "flds",
> - "(bad)",
> - "fsts",
> - "fstps",
> - "fldenv",
> - "fldcw",
> - "fNstenv",
> - "fNstcw",
> - /* da */
> - "fiaddl",
> - "fimull",
> - "ficoml",
> - "ficompl",
> - "fisubl",
> - "fisubrl",
> - "fidivl",
> - "fidivrl",
> - /* db */
> - "fildl",
> - "(bad)",
> - "fistl",
> - "fistpl",
> - "(bad)",
> - "fldt",
> - "(bad)",
> - "fstpt",
> - /* dc */
> - "faddl",
> - "fmull",
> - "fcoml",
> - "fcompl",
> - "fsubl",
> - "fsubrl",
> - "fdivl",
> - "fdivrl",
> - /* dd */
> - "fldl",
> - "(bad)",
> - "fstl",
> - "fstpl",
> - "frstor",
> - "(bad)",
> - "fNsave",
> - "fNstsw",
> - /* de */
> - "fiadd",
> - "fimul",
> - "ficom",
> - "ficomp",
> - "fisub",
> - "fisubr",
> - "fidiv",
> - "fidivr",
> - /* df */
> - "fild",
> - "(bad)",
> - "fist",
> - "fistp",
> - "fbld",
> - "fildll",
> - "fbstp",
> - "fistpll",
> -};
> -
> -#define ST OP_ST, 0
> -#define STi OP_STi, 0
> -int OP_ST(), OP_STi();
> -
> -#define FGRPd9_2 NULL, NULL, 0
> -#define FGRPd9_4 NULL, NULL, 1
> -#define FGRPd9_5 NULL, NULL, 2
> -#define FGRPd9_6 NULL, NULL, 3
> -#define FGRPd9_7 NULL, NULL, 4
> -#define FGRPda_5 NULL, NULL, 5
> -#define FGRPdb_4 NULL, NULL, 6
> -#define FGRPde_3 NULL, NULL, 7
> -#define FGRPdf_4 NULL, NULL, 8
> -
> -struct dis386 float_reg[][8] = {
> - /* d8 */
> - {
> - { "fadd", ST, STi },
> - { "fmul", ST, STi },
> - { "fcom", STi },
> - { "fcomp", STi },
> - { "fsub", ST, STi },
> - { "fsubr", ST, STi },
> - { "fdiv", ST, STi },
> - { "fdivr", ST, STi },
> - },
> - /* d9 */
> - {
> - { "fld", STi },
> - { "fxch", STi },
> - { FGRPd9_2 },
> - { "(bad)" },
> - { FGRPd9_4 },
> - { FGRPd9_5 },
> - { FGRPd9_6 },
> - { FGRPd9_7 },
> - },
> - /* da */
> - {
> - { "fcmovb", ST, STi },
> - { "fcmove", ST, STi },
> - { "fcmovbe",ST, STi },
> - { "fcmovu", ST, STi },
> - { "(bad)" },
> - { FGRPda_5 },
> - { "(bad)" },
> - { "(bad)" },
> - },
> - /* db */
> - {
> - { "fcmovnb",ST, STi },
> - { "fcmovne",ST, STi },
> - { "fcmovnbe",ST, STi },
> - { "fcmovnu",ST, STi },
> - { FGRPdb_4 },
> - { "fucomi", ST, STi },
> - { "fcomi", ST, STi },
> - { "(bad)" },
> - },
> - /* dc */
> - {
> - { "fadd", STi, ST },
> - { "fmul", STi, ST },
> - { "(bad)" },
> - { "(bad)" },
> - { "fsub", STi, ST },
> - { "fsubr", STi, ST },
> - { "fdiv", STi, ST },
> - { "fdivr", STi, ST },
> - },
> - /* dd */
> - {
> - { "ffree", STi },
> - { "(bad)" },
> - { "fst", STi },
> - { "fstp", STi },
> - { "fucom", STi },
> - { "fucomp", STi },
> - { "(bad)" },
> - { "(bad)" },
> - },
> - /* de */
> - {
> - { "faddp", STi, ST },
> - { "fmulp", STi, ST },
> - { "(bad)" },
> - { FGRPde_3 },
> - { "fsubp", STi, ST },
> - { "fsubrp", STi, ST },
> - { "fdivp", STi, ST },
> - { "fdivrp", STi, ST },
> - },
> - /* df */
> - {
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { "(bad)" },
> - { FGRPdf_4 },
> - { "fucomip",ST, STi },
> - { "fcomip", ST, STi },
> - { "(bad)" },
> - },
> -};
> -
> -
> -char *fgrps[][8] = {
> - /* d9_2 0 */
> - {
> - "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
> - },
> -
> - /* d9_4 1 */
> - {
> - "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
> - },
> -
> - /* d9_5 2 */
> - {
> - "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
> - },
> -
> - /* d9_6 3 */
> - {
> - "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
> - },
> -
> - /* d9_7 4 */
> - {
> - "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
> - },
> -
> - /* da_5 5 */
> - {
> - "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
> - },
> -
> - /* db_4 6 */
> - {
> - "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
> - "fNsetpm(287 only)","(bad)","(bad)","(bad)",
> - },
> -
> - /* de_3 7 */
> - {
> - "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
> - },
> -
> - /* df_4 8 */
> - {
> - "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
> - },
> -};
> -
> -static void
> -dofloat ()
> -{
> - struct dis386 *dp;
> - unsigned char floatop;
> -
> - floatop = codep[-1];
> -
> - if (mod != 3)
> - {
> - putop (float_mem[(floatop - 0xd8) * 8 + reg]);
> - obufp = op1out;
> - OP_E (v_mode);
> - return;
> - }
> - codep++;
> -
> - dp = &float_reg[floatop - 0xd8][reg];
> - if (dp->name == NULL)
> - {
> - putop (fgrps[dp->bytemode1][rm]);
> - /* instruction fnstsw is only one with strange arg */
> - if (floatop == 0xdf
> - && FETCH_DATA (the_info, codep + 1)
> - && *codep == 0xe0)
> - strcpy (op1out, "%eax");
> - }
> - else
> - {
> - putop (dp->name);
> - obufp = op1out;
> - if (dp->op1)
> - (*dp->op1)(dp->bytemode1);
> - obufp = op2out;
> - if (dp->op2)
> - (*dp->op2)(dp->bytemode2);
> - }
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_ST (ignore)
> - int ignore;
> -{
> - oappend ("%st");
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_STi (ignore)
> - int ignore;
> -{
> - sprintf (scratchbuf, "%%st(%d)", rm);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -
> -/* capital letters in template are macros */
> -static void
> -putop (template)
> - char *template;
> -{
> - char *p;
> -
> - for (p = template; *p; p++)
> - {
> - switch (*p)
> - {
> - default:
> - *obufp++ = *p;
> - break;
> - case 'C': /* For jcxz/jecxz */
> - if (aflag)
> - *obufp++ = 'e';
> - break;
> - case 'N':
> - if ((prefixes & PREFIX_FWAIT) == 0)
> - *obufp++ = 'n';
> - break;
> - case 'S':
> - /* operand size flag */
> - if (dflag)
> - *obufp++ = 'l';
> - else
> - *obufp++ = 'w';
> - break;
> - }
> - }
> - *obufp = 0;
> -}
> -
> -static void
> -oappend (s)
> - char *s;
> -{
> - strcpy (obufp, s);
> - obufp += strlen (s);
> - *obufp = 0;
> -}
> -
> -static void
> -append_prefix ()
> -{
> - if (prefixes & PREFIX_CS)
> - oappend ("%cs:");
> - if (prefixes & PREFIX_DS)
> - oappend ("%ds:");
> - if (prefixes & PREFIX_SS)
> - oappend ("%ss:");
> - if (prefixes & PREFIX_ES)
> - oappend ("%es:");
> - if (prefixes & PREFIX_FS)
> - oappend ("%fs:");
> - if (prefixes & PREFIX_GS)
> - oappend ("%gs:");
> -}
> -
> -int
> -OP_indirE (bytemode)
> - int bytemode;
> -{
> - oappend ("*");
> - return OP_E (bytemode);
> -}
> -
> -int
> -OP_E (bytemode)
> - int bytemode;
> -{
> - int disp;
> -
> - /* skip mod/rm byte */
> - codep++;
> -
> - if (mod == 3)
> - {
> - switch (bytemode)
> - {
> - case b_mode:
> - oappend (names8[rm]);
> - break;
> - case w_mode:
> - oappend (names16[rm]);
> - break;
> - case v_mode:
> - if (dflag)
> - oappend (names32[rm]);
> - else
> - oappend (names16[rm]);
> - break;
> - default:
> - oappend ("<bad dis table>");
> - break;
> - }
> - return 0;
> - }
> -
> - disp = 0;
> - append_prefix ();
> -
> - if (aflag) /* 32 bit address mode */
> - {
> - int havesib;
> - int havebase;
> - int base;
> - int index;
> - int scale;
> -
> - havesib = 0;
> - havebase = 1;
> - base = rm;
> -
> - if (base == 4)
> - {
> - havesib = 1;
> - FETCH_DATA (the_info, codep + 1);
> - scale = (*codep >> 6) & 3;
> - index = (*codep >> 3) & 7;
> - base = *codep & 7;
> - codep++;
> - }
> -
> - switch (mod)
> - {
> - case 0:
> - if (base == 5)
> - {
> - havebase = 0;
> - disp = get32 ();
> - }
> - break;
> - case 1:
> - FETCH_DATA (the_info, codep + 1);
> - disp = *(char *)codep++;
> - break;
> - case 2:
> - disp = get32 ();
> - break;
> - }
> -
> - if (mod != 0 || base == 5)
> - {
> - sprintf (scratchbuf, "0x%x", disp);
> - oappend (scratchbuf);
> - }
> -
> - if (havebase || (havesib && (index != 4 || scale != 0)))
> - {
> - oappend ("(");
> - if (havebase)
> - oappend (names32[base]);
> - if (havesib)
> - {
> - if (index != 4)
> - {
> - sprintf (scratchbuf, ",%s", names32[index]);
> - oappend (scratchbuf);
> - }
> - sprintf (scratchbuf, ",%d", 1 << scale);
> - oappend (scratchbuf);
> - }
> - oappend (")");
> - }
> - }
> - else
> - { /* 16 bit address mode */
> - switch (mod)
> - {
> - case 0:
> - if (rm == 6)
> - disp = (short) get16 ();
> - break;
> - case 1:
> - FETCH_DATA (the_info, codep + 1);
> - disp = *(char *)codep++;
> - break;
> - case 2:
> - disp = (short) get16 ();
> - break;
> - }
> -
> - if (mod != 0 || rm == 6)
> - {
> - sprintf (scratchbuf, "0x%x", disp);
> - oappend (scratchbuf);
> - }
> -
> - if (mod != 0 || rm != 6)
> - {
> - oappend ("(");
> - oappend (index16[rm]);
> - oappend (")");
> - }
> - }
> - return 0;
> -}
> -
> -int
> -OP_G (bytemode)
> - int bytemode;
> -{
> - switch (bytemode)
> - {
> - case b_mode:
> - oappend (names8[reg]);
> - break;
> - case w_mode:
> - oappend (names16[reg]);
> - break;
> - case d_mode:
> - oappend (names32[reg]);
> - break;
> - case v_mode:
> - if (dflag)
> - oappend (names32[reg]);
> - else
> - oappend (names16[reg]);
> - break;
> - default:
> - oappend ("<internal disassembler error>");
> - break;
> - }
> - return (0);
> -}
> -
> -static int
> -get32 ()
> -{
> - int x = 0;
> -
> - FETCH_DATA (the_info, codep + 4);
> - x = *codep++ & 0xff;
> - x |= (*codep++ & 0xff) << 8;
> - x |= (*codep++ & 0xff) << 16;
> - x |= (*codep++ & 0xff) << 24;
> - return (x);
> -}
> -
> -static int
> -get16 ()
> -{
> - int x = 0;
> -
> - FETCH_DATA (the_info, codep + 2);
> - x = *codep++ & 0xff;
> - x |= (*codep++ & 0xff) << 8;
> - return (x);
> -}
> -
> -static void
> -set_op (op)
> - int op;
> -{
> - op_index[op_ad] = op_ad;
> - op_address[op_ad] = op;
> -}
> -
> -int
> -OP_REG (code)
> - int code;
> -{
> - char *s;
> -
> - switch (code)
> - {
> - case indir_dx_reg: s = "(%dx)"; break;
> - case ax_reg: case cx_reg: case dx_reg: case bx_reg:
> - case sp_reg: case bp_reg: case si_reg: case di_reg:
> - s = names16[code - ax_reg];
> - break;
> - case es_reg: case ss_reg: case cs_reg:
> - case ds_reg: case fs_reg: case gs_reg:
> - s = names_seg[code - es_reg];
> - break;
> - case al_reg: case ah_reg: case cl_reg: case ch_reg:
> - case dl_reg: case dh_reg: case bl_reg: case bh_reg:
> - s = names8[code - al_reg];
> - break;
> - case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
> - case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
> - if (dflag)
> - s = names32[code - eAX_reg];
> - else
> - s = names16[code - eAX_reg];
> - break;
> - default:
> - s = "<internal disassembler error>";
> - break;
> - }
> - oappend (s);
> - return (0);
> -}
> -
> -int
> -OP_I (bytemode)
> - int bytemode;
> -{
> - int op;
> -
> - switch (bytemode)
> - {
> - case b_mode:
> - FETCH_DATA (the_info, codep + 1);
> - op = *codep++ & 0xff;
> - break;
> - case v_mode:
> - if (dflag)
> - op = get32 ();
> - else
> - op = get16 ();
> - break;
> - case w_mode:
> - op = get16 ();
> - break;
> - default:
> - oappend ("<internal disassembler error>");
> - return (0);
> - }
> - sprintf (scratchbuf, "$0x%x", op);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -int
> -OP_sI (bytemode)
> - int bytemode;
> -{
> - int op;
> -
> - switch (bytemode)
> - {
> - case b_mode:
> - FETCH_DATA (the_info, codep + 1);
> - op = *(char *)codep++;
> - break;
> - case v_mode:
> - if (dflag)
> - op = get32 ();
> - else
> - op = (short)get16();
> - break;
> - case w_mode:
> - op = (short)get16 ();
> - break;
> - default:
> - oappend ("<internal disassembler error>");
> - return (0);
> - }
> - sprintf (scratchbuf, "$0x%x", op);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -int
> -OP_J (bytemode)
> - int bytemode;
> -{
> - int disp;
> - int mask = -1;
> -
> - switch (bytemode)
> - {
> - case b_mode:
> - FETCH_DATA (the_info, codep + 1);
> - disp = *(char *)codep++;
> - break;
> - case v_mode:
> - if (dflag)
> - disp = get32 ();
> - else
> - {
> - disp = (short)get16 ();
> - /* for some reason, a data16 prefix on a jump instruction
> - means that the pc is masked to 16 bits after the
> - displacement is added! */
> - mask = 0xffff;
> - }
> - break;
> - default:
> - oappend ("<internal disassembler error>");
> - return (0);
> - }
> - disp = (start_pc + codep - start_codep + disp) & mask;
> - set_op (disp);
> - sprintf (scratchbuf, "0x%x", disp);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_SEG (dummy)
> - int dummy;
> -{
> - static char *sreg[] = {
> - "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
> - };
> -
> - oappend (sreg[reg]);
> - return (0);
> -}
> -
> -int
> -OP_DIR (size)
> - int size;
> -{
> - int seg, offset;
> -
> - switch (size)
> - {
> - case lptr:
> - if (aflag)
> - {
> - offset = get32 ();
> - seg = get16 ();
> - }
> - else
> - {
> - offset = get16 ();
> - seg = get16 ();
> - }
> - sprintf (scratchbuf, "0x%x,0x%x", seg, offset);
> - oappend (scratchbuf);
> - break;
> - case v_mode:
> - if (aflag)
> - offset = get32 ();
> - else
> - offset = (short)get16 ();
> -
> - offset = start_pc + codep - start_codep + offset;
> - set_op (offset);
> - sprintf (scratchbuf, "0x%x", offset);
> - oappend (scratchbuf);
> - break;
> - default:
> - oappend ("<internal disassembler error>");
> - break;
> - }
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_OFF (bytemode)
> - int bytemode;
> -{
> - int off;
> -
> - if (aflag)
> - off = get32 ();
> - else
> - off = get16 ();
> -
> - sprintf (scratchbuf, "0x%x", off);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_ESDI (dummy)
> - int dummy;
> -{
> - oappend ("%es:(");
> - oappend (aflag ? "%edi" : "%di");
> - oappend (")");
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_DSSI (dummy)
> - int dummy;
> -{
> - oappend ("%ds:(");
> - oappend (aflag ? "%esi" : "%si");
> - oappend (")");
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_ONE (dummy)
> - int dummy;
> -{
> - oappend ("1");
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_C (dummy)
> - int dummy;
> -{
> - codep++; /* skip mod/rm */
> - sprintf (scratchbuf, "%%cr%d", reg);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_D (dummy)
> - int dummy;
> -{
> - codep++; /* skip mod/rm */
> - sprintf (scratchbuf, "%%db%d", reg);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -/* ARGSUSED */
> -int
> -OP_T (dummy)
> - int dummy;
> -{
> - codep++; /* skip mod/rm */
> - sprintf (scratchbuf, "%%tr%d", reg);
> - oappend (scratchbuf);
> - return (0);
> -}
> -
> -int
> -OP_rm (bytemode)
> - int bytemode;
> -{
> - switch (bytemode)
> - {
> - case d_mode:
> - oappend (names32[rm]);
> - break;
> - case w_mode:
> - oappend (names16[rm]);
> - break;
> - }
> - return (0);
> -}
> diff --git a/opcode/i386.h b/opcode/i386.h
> deleted file mode 100644
> index fe6211b..0000000
> --- a/opcode/i386.h
> +++ /dev/null
> @@ -1,898 +0,0 @@
> -/* i386-opcode.h -- Intel 80386 opcode table
> - Copyright 1989, 1991, 1992, 1995 Free Software Foundation.
> -
> -This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
> -
> -This program is free software; you can redistribute it and/or modify
> -it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 2 of the License, or
> -(at your option) any later version.
> -
> -This program is distributed in the hope that it will be useful,
> -but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this program; if not, write to the Free Software
> -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -static const template i386_optab[] = {
> -
> -#define _ None
> -/* move instructions */
> -#define MOV_AX_DISP32 0xa0
> -{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } },
> -{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
> -{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
> -{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } },
> -{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, Reg16|Mem, 0 } },
> -/* move to/from control debug registers */
> -{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
> -{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
> -{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} },
> -
> -/* move with sign extend */
> -/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
> - conflict with the "movs" string move instruction. Thus,
> - {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32,
> 0} },
> - is not kosher; we must seperate the two instructions. */
> -{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32,
> 0} },
> -{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16,
> 0} },
> -{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
> -
> -/* move with zero extend */
> -{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0}
> },
> -{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
> -
> -/* push instructions */
> -{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } },
> -{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } },
> -{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} },
> -{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} },
> -{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } },
> -{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } },
> -/* push all */
> -{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } },
> -
> -/* pop instructions */
> -{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } },
> -{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } },
> -#define POP_SEG_SHORT 0x7
> -{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } },
> -{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } },
> -/* pop all */
> -{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } },
> -
> -/* xchg exchange instructions
> - xchg commutes: we allow both operand orders */
> -{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } },
> -{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } },
> -{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } },
> -{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } },
> -
> -/* in/out from ports */
> -{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } },
> -{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } },
> -{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } },
> -{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } },
> -{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } },
> -{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } },
> -{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } },
> -{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } },
> -
> -/* load effective address */
> -{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } },
> -
> -/* load segment registers from memory */
> -{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} },
> -{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} },
> -{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} },
> -{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} },
> -{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} },
> -
> -/* flags register instructions */
> -{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} },
> -{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} },
> -{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} },
> -{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} },
> -{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} },
> -{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} },
> -{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} },
> -{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} },
> -{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} },
> -{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} },
> -{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} },
> -{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} },
> -{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} },
> -{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} },
> -{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} },
> -{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} },
> -
> -{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} },
> -{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} },
> -{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} },
> -{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} },
> -{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} },
> -{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} },
> -{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} },
> -{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} },
> -{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} },
> -{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} },
> -{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} },
> -{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} },
> -{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} },
> -{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} },
> -{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} },
> -{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} },
> -
> -{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
> -{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} },
> -{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} },
> -{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} },
> -{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} },
> -{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} },
> -{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} },
> -
> -/* conversion insns */
> -/* conversion: intel naming */
> -{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
> -{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
> -{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
> -{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
> -/* att naming */
> -{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
> -{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
> -{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
> -{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
> -
> -/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
> - expanding 64-bit multiplies, and *cannot* be selected to accomplish
> - 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
> - These multiplies can only be selected with single operand forms. */
> -{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
> -{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -
> -
> -
> -/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
> - These instructions are exceptions: 'imul $2, %eax, %ecx' would put
> - '%eax' in the reg field and '%ecx' in the regmem field if we did not
> - switch them. */
> -{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
> -{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg}
> },
> -{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem,
> WordReg} },
> -/*
> - imul with 2 operands mimicks imul with 3 by puting register both
> - in i.rm.reg & i.rm.regmem fields
> -*/
> -{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} },
> -{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
> -{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
> -{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
> -{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
> -{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
> -
> -{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
> -{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
> -{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
> -{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} },
> -
> -{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
> -{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
> -{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} },
> -
> -{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
> -{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
> -{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
> -{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
> -
> -/* control transfer instructions */
> -#define CALL_PC_RELATIVE 0xe8
> -{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} },
> -{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} },
> -{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} },
> -#define CALL_FAR_IMMEDIATE 0x9a
> -{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Abs32|Imm32, 0} },
> -{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} },
> -{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} },
> -
> -#define JUMP_PC_RELATIVE 0xeb
> -{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} },
> -{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
> -#define JUMP_FAR_IMMEDIATE 0xea
> -{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} },
> -{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} },
> -
> -{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} },
> -{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} },
> -{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} },
> -{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} },
> -{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} },
> -{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} },
> -{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} },
> -{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} },
> -{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} },
> -{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} },
> -{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} },
> -{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} },
> -
> -/* conditional jumps */
> -{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} },
> -
> -{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} },
> -
> -{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} },
> -{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} },
> -{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} },
> -
> -{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} },
> -{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} },
> -{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} },
> -
> -{"je", 1, 0x74, _, Jump, { Disp, 0, 0} },
> -{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} },
> -
> -{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} },
> -{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} },
> -
> -{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} },
> -{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} },
> -
> -{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} },
> -{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} },
> -
> -{"js", 1, 0x78, _, Jump, { Disp, 0, 0} },
> -
> -{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} },
> -
> -{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} },
> -{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} },
> -
> -{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} },
> -{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} },
> -
> -{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} },
> -{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} },
> -
> -{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} },
> -{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} },
> -
> -{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} },
> -{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} },
> -
> -{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
> -{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
> -
> -#if 0 /* XXX where are these macros used?
> - To get them working again, they need to take
> - an entire template as the parameter,
> - and check for Data16/Data32 flags. */
> -/* these turn into pseudo operations when disp is larger than 8 bits */
> -#define IS_JUMP_ON_CX_ZERO(o) \
> - (o == 0x66e3)
> -#define IS_JUMP_ON_ECX_ZERO(o) \
> - (o == 0xe3)
> -#endif
> -
> -{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} },
> -{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} },
> -
> -#define IS_LOOP_ECX_TIMES(o) \
> - (o == 0xe2 || o == 0xe1 || o == 0xe0)
> -
> -{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} },
> -
> -{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
> -{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
> -
> -{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
> -{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
> -
> -/* set byte on flag instructions */
> -{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
> -{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
> -
> -#define IS_STRING_INSTRUCTION(o) \
> - ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
> - (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
> - (o) == 0xd7)
> -
> -/* string manipulation */
> -{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
> -{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
> -{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} },
> -{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} },
> -{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
> -{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
> -{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
> -{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
> -{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
> -{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
> -{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
> -{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
> -{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} },
> -
> -/* bit manipulation */
> -{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
> -{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
> -{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} },
> -{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
> -{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} },
> -{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
> -{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} },
> -{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
> -{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} },
> -{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
> -
> -/* interrupts & op. sys insns */
> -/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
> - int 3 insn. */
> -#define INT_OPCODE 0xcd
> -#define INT3_OPCODE 0xcc
> -{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} },
> -{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} },
> -{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} },
> -{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} },
> -{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} },
> -/* i386sl, i486sl, later 486, and Pentium */
> -{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} },
> -
> -{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} },
> -{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} },
> -
> -{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} },
> -{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
> -/* nop is actually 'xchgl %eax, %eax' */
> -{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} },
> -
> -/* protection control */
> -{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} },
> -{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
> -{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
> -{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
> -{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
> -{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
> -{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
> -{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
> -
> -{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
> -{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
> -{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
> -{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
> -{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
> -
> -{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
> -{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
> -
> -/* floating point instructions */
> -
> -/* load */
> -{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
> -{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */
> -{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double
> */
> -{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
> -{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word
> (16) */
> -{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */
> -{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword
> (64) */
> -{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
> -{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat
> */
> -{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */
> -
> -/* store (no pop) */
> -{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
> -{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
> -{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double
> */
> -{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
> -{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word
> (16) */
> -{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
> -
> -/* store (with pop) */
> -{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
> -{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
> -{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
> -{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
> -{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
> -{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
> -{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
> -{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
> -{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */
> -{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */
> -
> -/* exchange %st<n> with %st0 */
> -{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1)
> */
> -
> -/* comparison (without pop) */
> -{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
> -{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem
> word */
> -{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
> -{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
> -{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem
> dword */
> -
> -/* comparison (with pop) */
> -{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem
> float */
> -{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem
> word */
> -{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem
> double */
> -{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
> -{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem
> dword */
> -{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 &
> pop 2 */
> -
> -/* unordered comparison (with pop) */
> -{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 &
> pop twice */
> -
> -{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */
> -{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */
> -
> -/* load constants into %st0 */
> -{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */
> -{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */
> -{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */
> -{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */
> -{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */
> -{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */
> -{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */
> -
> -/* arithmetic */
> -
> -/* add */
> -{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
> -{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1)
> */
> -{"faddp", 1, 0xdac0, _, ShortForm, { FloatReg, 0, 0} },
> -{"faddp", 2, 0xdac0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
> -{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st,
> %st(1) */
> -{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
> -{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
> -{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
> -{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
> -
> -/* sub */
> -/* Note: intel has decided that certain of these operations are reversed
> - in assembler syntax. */
> -{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} },
> -{"fsubp", 1, 0xdae0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fsubp", 2, 0xdae0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
> -{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
> -{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
> -{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
> -{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
> -
> -/* sub reverse */
> -{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} },
> -{"fsubrp", 1, 0xdae8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fsubrp", 2, 0xdae8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
> -{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
> -{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
> -{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
> -{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
> -
> -/* mul */
> -{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
> -{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} },
> -{"fmulp", 1, 0xdac8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fmulp", 2, 0xdac8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
> -{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} },
> -{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
> -{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
> -{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
> -{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
> -
> -/* div */
> -/* Note: intel has decided that certain of these operations are reversed
> - in assembler syntax. */
> -{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} },
> -{"fdivp", 1, 0xdaf0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fdivp", 2, 0xdaf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
> -{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
> -{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
> -{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
> -{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
> -
> -/* div reverse */
> -{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} },
> -{"fdivrp", 1, 0xdaf8, _, ShortForm, { FloatReg, 0, 0} },
> -{"fdivrp", 2, 0xdaf8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -#ifdef NON_BROKEN_OPCODES
> -{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#else
> -{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
> -#endif
> -{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
> -{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
> -{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
> -{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
> -{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
> -
> -{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} },
> -{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} },
> -{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} },
> -{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} },
> -{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} },
> -{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} },
> -{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} },
> -{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} },
> -{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} },
> -{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} },
> -{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} },
> -{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} },
> -{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} },
> -{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} },
> -{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} },
> -{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} },
> -
> -{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} },
> -{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
> -
> -/* processor control */
> -{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
> -{"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} },
> -{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
> -{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
> -{"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} },
> -{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
> -{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
> -{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
> -{"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} },
> -{"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} },
> -{"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} },
> -{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
> -{"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} },
> -/*
> - We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
> - instructions; i'm not sure how to add them or how they are different.
> - My 386/387 book offers no details about this.
> -*/
> -{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
> -{"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} },
> -{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
> -{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
> -{"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} },
> -{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
> -
> -{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
> -{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
> -{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
> -
> -/*
> - opcode prefixes; we allow them as seperate insns too
> - (see prefix table below)
> -*/
> -{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} },
> -{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} },
> -{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} },
> -{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} },
> -{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} },
> -{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} },
> -{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} },
> -{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} },
> -{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} },
> -{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} },
> -{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} },
> -{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
> -{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
> -{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
> -{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
> -{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
> -
> -/* 486 extensions */
> -
> -{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } },
> -{"xadd", 2, 0x0fc0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
> -{"cmpxchg", 2, 0x0fb0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
> -{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} },
> -{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} },
> -{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
> -
> -/* 586 and late 486 extensions */
> -{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} },
> -
> -/* Pentium extensions */
> -{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} },
> -{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} },
> -{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} },
> -{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} },
> -
> -/* Pentium Pro extensions */
> -{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} },
> -
> -{"cmovo", 2, 0x0f40, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovno", 2, 0x0f41, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovb", 2, 0x0f42, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovae", 2, 0x0f43, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmove", 2, 0x0f44, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovne", 2, 0x0f45, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovbe", 2, 0x0f46, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmova", 2, 0x0f47, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovs", 2, 0x0f48, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovns", 2, 0x0f49, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovp", 2, 0x0f4a, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovnp", 2, 0x0f4b, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovl", 2, 0x0f4c, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovge", 2, 0x0f4d, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovle", 2, 0x0f4e, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -{"cmovg", 2, 0x0f4f, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem,
> WordReg, 0} },
> -
> -{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -
> -{"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
> -
> -{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
> -};
> -#undef _
> -
> -static const template *const i386_optab_end
> - = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
> -
> -/* 386 register table */
> -
> -static const reg_entry i386_regtab[] = {
> - /* 8 bit regs */
> - {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
> - {"bl", Reg8, 3},
> - {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
> - /* 16 bit regs */
> - {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2},
> {"bx", Reg16, 3},
> - {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
> - /* 32 bit regs */
> - {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx",
> Reg32, 3},
> - {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
> - /* segment registers */
> - {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
> - {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
> - /* control registers */
> - {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
> - {"cr4", Control, 4},
> - /* debug registers */
> - {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
> - {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
> - {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2},
> - {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7},
> - /* test registers */
> - {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5},
> - {"tr6", Test, 6}, {"tr7", Test, 7},
> - /* float registers */
> - {"st(0)", FloatReg|FloatAcc, 0},
> - {"st", FloatReg|FloatAcc, 0},
> - {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
> - {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
> - {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
> -};
> -
> -#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
> -
> -static const reg_entry *const i386_regtab_end
> - = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
> -
> -/* segment stuff */
> -static const seg_entry cs = { "cs", 0x2e };
> -static const seg_entry ds = { "ds", 0x3e };
> -static const seg_entry ss = { "ss", 0x36 };
> -static const seg_entry es = { "es", 0x26 };
> -static const seg_entry fs = { "fs", 0x64 };
> -static const seg_entry gs = { "gs", 0x65 };
> -static const seg_entry null = { "", 0x0 };
> -
> -/*
> - This table is used to store the default segment register implied by all
> - possible memory addressing modes.
> - It is indexed by the mode & modrm entries of the modrm byte as follows:
> - index = (mode<<3) | modrm;
> -*/
> -static const seg_entry *const one_byte_segment_defaults[] = {
> - /* mode 0 */
> - &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
> - /* mode 1 */
> - &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
> - /* mode 2 */
> - &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
> - /* mode 3 --- not a memory reference; never referenced */
> -};
> -
> -static const seg_entry *const two_byte_segment_defaults[] = {
> - /* mode 0 */
> - &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
> - /* mode 1 */
> - &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
> - /* mode 2 */
> - &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
> - /* mode 3 --- not a memory reference; never referenced */
> -};
> -
> -static const prefix_entry i386_prefixtab[] = {
> -#define ADDR_PREFIX_OPCODE 0x67
> - { "addr16", 0x67 }, /* address size prefix ==> 16bit
> addressing
> - * (How is this useful?) */
> -#define WORD_PREFIX_OPCODE 0x66
> - { "data16", 0x66 }, /* operand size prefix */
> - { "lock", 0xf0 }, /* bus lock prefix */
> - { "wait", 0x9b }, /* wait for coprocessor */
> - { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
> - { "es", 0x26 }, { "fs", 0x64 },
> - { "gs", 0x65 }, { "ss", 0x36 },
> -/* REPE & REPNE used to detect rep/repne with a non-string instruction */
> -#define REPNE 0xf2
> -#define REPE 0xf3
> - { "rep", 0xf3 }, /* repeat string instructions */
> - { "repe", 0xf3 }, { "repz", 0xf3 },
> - { "repne", 0xf2 }, { "repnz", 0xf2 }
> -};
> -
> -static const prefix_entry *const i386_prefixtab_end
> - = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
> -
> -/* end of i386-opcode.h */
> diff --git a/opcode/ppc-dis.c b/opcode/ppc-dis.c
> deleted file mode 100644
> index 6a50151..0000000
> --- a/opcode/ppc-dis.c
> +++ /dev/null
> @@ -1,238 +0,0 @@
> -/* ppc-dis.c -- Disassemble PowerPC instructions
> - Copyright 1994 Free Software Foundation, Inc.
> - Written by Ian Lance Taylor, Cygnus Support
> -
> -This file is part of GDB, GAS, and the GNU binutils.
> -
> -GDB, GAS, and the GNU binutils are free software; you can redistribute
> -them and/or modify them under the terms of the GNU General Public
> -License as published by the Free Software Foundation; either version
> -2, or (at your option) any later version.
> -
> -GDB, GAS, and the GNU binutils are distributed in the hope that they
> -will be useful, but WITHOUT ANY WARRANTY; without even the implied
> -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> -the GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this file; see the file COPYING. If not, write to the Free
> -Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -#include <stdio.h>
> -#include "ansidecl.h"
> -#include "sysdep.h"
> -#include "dis-asm.h"
> -#include "opcode/ppc.h"
> -
> -/* This file provides several disassembler functions, all of which use
> - the disassembler interface defined in dis-asm.h. Several functions
> - are provided because this file handles disassembly for the PowerPC
> - in both big and little endian mode and also for the POWER (RS/6000)
> - chip. */
> -
> -static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
> - int bigendian, int dialect));
> -
> -/* Print a big endian PowerPC instruction. For convenience, also
> - disassemble instructions supported by the Motorola PowerPC 601. */
> -
> -int
> -print_insn_big_powerpc (memaddr, info)
> - bfd_vma memaddr;
> - struct disassemble_info *info;
> -{
> - return print_insn_powerpc (memaddr, info, 1,
> - PPC_OPCODE_PPC | PPC_OPCODE_601);
> -}
> -
> -/* Print a little endian PowerPC instruction. For convenience, also
> - disassemble instructions supported by the Motorola PowerPC 601. */
> -
> -int
> -print_insn_little_powerpc (memaddr, info)
> - bfd_vma memaddr;
> - struct disassemble_info *info;
> -{
> - return print_insn_powerpc (memaddr, info, 0,
> - PPC_OPCODE_PPC | PPC_OPCODE_601);
> -}
> -
> -/* Print a POWER (RS/6000) instruction. */
> -
> -int
> -print_insn_rs6000 (memaddr, info)
> - bfd_vma memaddr;
> - struct disassemble_info *info;
> -{
> - return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
> -}
> -
> -/* Print a PowerPC or POWER instruction. */
> -
> -static int
> -print_insn_powerpc (memaddr, info, bigendian, dialect)
> - bfd_vma memaddr;
> - struct disassemble_info *info;
> - int bigendian;
> - int dialect;
> -{
> - bfd_byte buffer[4];
> - int status;
> - unsigned long insn;
> - const struct powerpc_opcode *opcode;
> - const struct powerpc_opcode *opcode_end;
> - unsigned long op;
> -
> - status = (*info->read_memory_func) (memaddr, buffer, 4, info);
> - if (status != 0)
> - {
> - (*info->memory_error_func) (status, memaddr, info);
> - return -1;
> - }
> -
> - if (bigendian)
> - insn = bfd_getb32 (buffer);
> - else
> - insn = bfd_getl32 (buffer);
> -
> - /* Get the major opcode of the instruction. */
> - op = PPC_OP (insn);
> -
> - /* Find the first match in the opcode table. We could speed this up
> - a bit by doing a binary search on the major opcode. */
> - opcode_end = powerpc_opcodes + powerpc_num_opcodes;
> - for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
> - {
> - unsigned long table_op;
> - const unsigned char *opindex;
> - const struct powerpc_operand *operand;
> - int invalid;
> - int need_comma;
> - int need_paren;
> -
> - table_op = PPC_OP (opcode->opcode);
> - if (op < table_op)
> - break;
> - if (op > table_op)
> - continue;
> -
> - if ((insn & opcode->mask) != opcode->opcode
> - || (opcode->flags & dialect) == 0)
> - continue;
> -
> - /* Make two passes over the operands. First see if any of them
> - have extraction functions, and, if they do, make sure the
> - instruction is valid. */
> - invalid = 0;
> - for (opindex = opcode->operands; *opindex != 0; opindex++)
> - {
> - operand = powerpc_operands + *opindex;
> - if (operand->extract)
> - (*operand->extract) (insn, &invalid);
> - }
> - if (invalid)
> - continue;
> -
> - /* The instruction is valid. */
> - (*info->fprintf_func) (info->stream, "%s", opcode->name);
> - if (opcode->operands[0] != 0)
> - (*info->fprintf_func) (info->stream, "\t");
> -
> - /* Now extract and print the operands. */
> - need_comma = 0;
> - need_paren = 0;
> - for (opindex = opcode->operands; *opindex != 0; opindex++)
> - {
> - long value;
> -
> - operand = powerpc_operands + *opindex;
> -
> - /* Operands that are marked FAKE are simply ignored. We
> - already made sure that the extract function considered
> - the instruction to be valid. */
> - if ((operand->flags & PPC_OPERAND_FAKE) != 0)
> - continue;
> -
> - /* Extract the value from the instruction. */
> - if (operand->extract)
> - value = (*operand->extract) (insn, (int *) NULL);
> - else
> - {
> - value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
> - if ((operand->flags & PPC_OPERAND_SIGNED) != 0
> - && (value & (1 << (operand->bits - 1))) != 0)
> - value -= 1 << operand->bits;
> - }
> -
> - /* If the operand is optional, and the value is zero, don't
> - print anything. */
> - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
> - && (operand->flags & PPC_OPERAND_NEXT) == 0
> - && value == 0)
> - continue;
> -
> - if (need_comma)
> - {
> - (*info->fprintf_func) (info->stream, ",");
> - need_comma = 0;
> - }
> -
> - /* Print the operand as directed by the flags. */
> - if ((operand->flags & PPC_OPERAND_GPR) != 0)
> - (*info->fprintf_func) (info->stream, "r%ld", value);
> - else if ((operand->flags & PPC_OPERAND_FPR) != 0)
> - (*info->fprintf_func) (info->stream, "f%ld", value);
> - else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
> - (*info->print_address_func) (memaddr + value, info);
> - else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
> - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
> - else if ((operand->flags & PPC_OPERAND_CR) == 0
> - || (dialect & PPC_OPCODE_PPC) == 0)
> - (*info->fprintf_func) (info->stream, "%ld", value);
> - else
> - {
> - if (operand->bits == 3)
> - (*info->fprintf_func) (info->stream, "cr%d", value);
> - else
> - {
> - static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
> - int cr;
> - int cc;
> -
> - cr = value >> 2;
> - if (cr != 0)
> - (*info->fprintf_func) (info->stream, "4*cr%d", cr);
> - cc = value & 3;
> - if (cc != 0)
> - {
> - if (cr != 0)
> - (*info->fprintf_func) (info->stream, "+");
> - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
> - }
> - }
> - }
> -
> - if (need_paren)
> - {
> - (*info->fprintf_func) (info->stream, ")");
> - need_paren = 0;
> - }
> -
> - if ((operand->flags & PPC_OPERAND_PARENS) == 0)
> - need_comma = 1;
> - else
> - {
> - (*info->fprintf_func) (info->stream, "(");
> - need_paren = 1;
> - }
> - }
> -
> - /* We have found and printed an instruction; return. */
> - return 4;
> - }
> -
> - /* We could not find a match. */
> - (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
> -
> - return 4;
> -}
> diff --git a/opcode/ppc-opc.c b/opcode/ppc-opc.c
> deleted file mode 100644
> index 5715415..0000000
> --- a/opcode/ppc-opc.c
> +++ /dev/null
> @@ -1,2830 +0,0 @@
> -/* ppc-opc.c -- PowerPC opcode list
> - Copyright 1994 Free Software Foundation, Inc.
> - Written by Ian Lance Taylor, Cygnus Support
> -
> -This file is part of GDB, GAS, and the GNU binutils.
> -
> -GDB, GAS, and the GNU binutils are free software; you can redistribute
> -them and/or modify them under the terms of the GNU General Public
> -License as published by the Free Software Foundation; either version
> -2, or (at your option) any later version.
> -
> -GDB, GAS, and the GNU binutils are distributed in the hope that they
> -will be useful, but WITHOUT ANY WARRANTY; without even the implied
> -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> -the GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this file; see the file COPYING. If not, write to the Free
> -Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -#include <stdio.h>
> -#include "ansidecl.h"
> -#include "opcode/ppc.h"
> -
> -/* This file holds the PowerPC opcode table. The opcode table
> - includes almost all of the extended instruction mnemonics. This
> - permits the disassembler to use them, and simplifies the assembler
> - logic, at the cost of increasing the table size. The table is
> - strictly constant data, so the compiler should be able to put it in
> - the .text section.
> -
> - This file also holds the operand table. All knowledge about
> - inserting operands into instructions and vice-versa is kept in this
> - file. */
> -
> -/* Local insertion and extraction functions. */
> -
> -static unsigned long insert_bat PARAMS ((unsigned long, long, const char
> **));
> -static long extract_bat PARAMS ((unsigned long, int *));
> -static unsigned long insert_bba PARAMS ((unsigned long, long, const char
> **));
> -static long extract_bba PARAMS ((unsigned long, int *));
> -static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
> -static long extract_bd PARAMS ((unsigned long, int *));
> -static unsigned long insert_bdm PARAMS ((unsigned long, long, const char
> **));
> -static long extract_bdm PARAMS ((unsigned long, int *));
> -static unsigned long insert_bdp PARAMS ((unsigned long, long, const char
> **));
> -static long extract_bdp PARAMS ((unsigned long, int *));
> -static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
> -static long extract_bo PARAMS ((unsigned long, int *));
> -static unsigned long insert_boe PARAMS ((unsigned long, long, const char
> **));
> -static long extract_boe PARAMS ((unsigned long, int *));
> -static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
> -static long extract_ds PARAMS ((unsigned long, int *));
> -static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
> -static long extract_li PARAMS ((unsigned long, int *));
> -static unsigned long insert_mbe PARAMS ((unsigned long, long, const char
> **));
> -static long extract_mbe PARAMS ((unsigned long, int *));
> -static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char
> **));
> -static long extract_mb6 PARAMS ((unsigned long, int *));
> -static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
> -static long extract_nb PARAMS ((unsigned long, int *));
> -static unsigned long insert_nsi PARAMS ((unsigned long, long, const char
> **));
> -static long extract_nsi PARAMS ((unsigned long, int *));
> -static unsigned long insert_ral PARAMS ((unsigned long, long, const char
> **));
> -static unsigned long insert_ram PARAMS ((unsigned long, long, const char
> **));
> -static unsigned long insert_ras PARAMS ((unsigned long, long, const char
> **));
> -static unsigned long insert_rbs PARAMS ((unsigned long, long, const char
> **));
> -static long extract_rbs PARAMS ((unsigned long, int *));
> -static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char
> **));
> -static long extract_sh6 PARAMS ((unsigned long, int *));
> -static unsigned long insert_spr PARAMS ((unsigned long, long, const char
> **));
> -static long extract_spr PARAMS ((unsigned long, int *));
> -static unsigned long insert_tbr PARAMS ((unsigned long, long, const char
> **));
> -static long extract_tbr PARAMS ((unsigned long, int *));
> -
> -/* The operands table.
> -
> - The fields are bits, shift, signed, insert, extract, flags. */
> -
> -const struct powerpc_operand powerpc_operands[] =
> -{
> - /* The zero index is used to indicate the end of the list of
> - operands. */
> -#define UNUSED (0)
> - { 0, 0, 0, 0, 0 },
> -
> - /* The BA field in an XL form instruction. */
> -#define BA (UNUSED + 1)
> -#define BA_MASK (0x1f << 16)
> - { 5, 16, 0, 0, PPC_OPERAND_CR },
> -
> - /* The BA field in an XL form instruction when it must be the same
> - as the BT field in the same instruction. */
> -#define BAT (BA + 1)
> - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
> -
> - /* The BB field in an XL form instruction. */
> -#define BB (BAT + 1)
> -#define BB_MASK (0x1f << 11)
> - { 5, 11, 0, 0, PPC_OPERAND_CR },
> -
> - /* The BB field in an XL form instruction when it must be the same
> - as the BA field in the same instruction. */
> -#define BBA (BB + 1)
> - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
> -
> - /* The BD field in a B form instruction. The lower two bits are
> - forced to zero. */
> -#define BD (BBA + 1)
> - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED
> },
> -
> - /* The BD field in a B form instruction when absolute addressing is
> - used. */
> -#define BDA (BD + 1)
> - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED
> },
> -
> - /* The BD field in a B form instruction when the - modifier is used.
> - This sets the y bit of the BO field appropriately. */
> -#define BDM (BDA + 1)
> - { 16, 0, insert_bdm, extract_bdm,
> - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
> -
> - /* The BD field in a B form instruction when the - modifier is used
> - and absolute address is used. */
> -#define BDMA (BDM + 1)
> - { 16, 0, insert_bdm, extract_bdm,
> - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
> -
> - /* The BD field in a B form instruction when the + modifier is used.
> - This sets the y bit of the BO field appropriately. */
> -#define BDP (BDMA + 1)
> - { 16, 0, insert_bdp, extract_bdp,
> - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
> -
> - /* The BD field in a B form instruction when the + modifier is used
> - and absolute addressing is used. */
> -#define BDPA (BDP + 1)
> - { 16, 0, insert_bdp, extract_bdp,
> - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
> -
> - /* The BF field in an X or XL form instruction. */
> -#define BF (BDPA + 1)
> - { 3, 23, 0, 0, PPC_OPERAND_CR },
> -
> - /* An optional BF field. This is used for comparison instructions,
> - in which an omitted BF field is taken as zero. */
> -#define OBF (BF + 1)
> - { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
> -
> - /* The BFA field in an X or XL form instruction. */
> -#define BFA (OBF + 1)
> - { 3, 18, 0, 0, PPC_OPERAND_CR },
> -
> - /* The BI field in a B form or XL form instruction. */
> -#define BI (BFA + 1)
> -#define BI_MASK (0x1f << 16)
> - { 5, 16, 0, 0, PPC_OPERAND_CR },
> -
> - /* The BO field in a B form instruction. Certain values are
> - illegal. */
> -#define BO (BI + 1)
> -#define BO_MASK (0x1f << 21)
> - { 5, 21, insert_bo, extract_bo, 0 },
> -
> - /* The BO field in a B form instruction when the + or - modifier is
> - used. This is like the BO field, but it must be even. */
> -#define BOE (BO + 1)
> - { 5, 21, insert_boe, extract_boe, 0 },
> -
> - /* The BT field in an X or XL form instruction. */
> -#define BT (BOE + 1)
> - { 5, 21, 0, 0, PPC_OPERAND_CR },
> -
> - /* The condition register number portion of the BI field in a B form
> - or XL form instruction. This is used for the extended
> - conditional branch mnemonics, which set the lower two bits of the
> - BI field. This field is optional. */
> -#define CR (BT + 1)
> - { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
> -
> - /* The D field in a D form instruction. This is a displacement off
> - a register, and implies that the next operand is a register in
> - parentheses. */
> -#define D (CR + 1)
> - { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
> -
> - /* The DS field in a DS form instruction. This is like D, but the
> - lower two bits are forced to zero. */
> -#define DS (D + 1)
> - { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
> -
> - /* The FL1 field in a POWER SC form instruction. */
> -#define FL1 (DS + 1)
> - { 4, 12, 0, 0, 0 },
> -
> - /* The FL2 field in a POWER SC form instruction. */
> -#define FL2 (FL1 + 1)
> - { 3, 2, 0, 0, 0 },
> -
> - /* The FLM field in an XFL form instruction. */
> -#define FLM (FL2 + 1)
> - { 8, 17, 0, 0, 0 },
> -
> - /* The FRA field in an X or A form instruction. */
> -#define FRA (FLM + 1)
> -#define FRA_MASK (0x1f << 16)
> - { 5, 16, 0, 0, PPC_OPERAND_FPR },
> -
> - /* The FRB field in an X or A form instruction. */
> -#define FRB (FRA + 1)
> -#define FRB_MASK (0x1f << 11)
> - { 5, 11, 0, 0, PPC_OPERAND_FPR },
> -
> - /* The FRC field in an A form instruction. */
> -#define FRC (FRB + 1)
> -#define FRC_MASK (0x1f << 6)
> - { 5, 6, 0, 0, PPC_OPERAND_FPR },
> -
> - /* The FRS field in an X form instruction or the FRT field in a D, X
> - or A form instruction. */
> -#define FRS (FRC + 1)
> -#define FRT (FRS)
> - { 5, 21, 0, 0, PPC_OPERAND_FPR },
> -
> - /* The FXM field in an XFX instruction. */
> -#define FXM (FRS + 1)
> -#define FXM_MASK (0xff << 12)
> - { 8, 12, 0, 0, 0 },
> -
> - /* The L field in a D or X form instruction. */
> -#define L (FXM + 1)
> - { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
> -
> - /* The LEV field in a POWER SC form instruction. */
> -#define LEV (L + 1)
> - { 7, 5, 0, 0, 0 },
> -
> - /* The LI field in an I form instruction. The lower two bits are
> - forced to zero. */
> -#define LI (LEV + 1)
> - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED
> },
> -
> - /* The LI field in an I form instruction when used as an absolute
> - address. */
> -#define LIA (LI + 1)
> - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED
> },
> -
> - /* The MB field in an M form instruction. */
> -#define MB (LIA + 1)
> -#define MB_MASK (0x1f << 6)
> - { 5, 6, 0, 0, 0 },
> -
> - /* The ME field in an M form instruction. */
> -#define ME (MB + 1)
> -#define ME_MASK (0x1f << 1)
> - { 5, 1, 0, 0, 0 },
> -
> - /* The MB and ME fields in an M form instruction expressed a single
> - operand which is a bitmask indicating which bits to select. This
> - is a two operand form using PPC_OPERAND_NEXT. See the
> - description in opcode/ppc.h for what this means. */
> -#define MBE (ME + 1)
> - { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
> - { 32, 0, insert_mbe, extract_mbe, 0 },
> -
> - /* The MB or ME field in an MD or MDS form instruction. The high
> - bit is wrapped to the low end. */
> -#define MB6 (MBE + 2)
> -#define ME6 (MB6)
> -#define MB6_MASK (0x3f << 5)
> - { 6, 5, insert_mb6, extract_mb6, 0 },
> -
> - /* The NB field in an X form instruction. The value 32 is stored as
> - 0. */
> -#define NB (MB6 + 1)
> - { 6, 11, insert_nb, extract_nb, 0 },
> -
> - /* The NSI field in a D form instruction. This is the same as the
> - SI field, only negated. */
> -#define NSI (NB + 1)
> - { 16, 0, insert_nsi, extract_nsi,
> - PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
> -
> - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
> -#define RA (NSI + 1)
> -#define RA_MASK (0x1f << 16)
> - { 5, 16, 0, 0, PPC_OPERAND_GPR },
> -
> - /* The RA field in a D or X form instruction which is an updating
> - load, which means that the RA field may not be zero and may not
> - equal the RT field. */
> -#define RAL (RA + 1)
> - { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
> -
> - /* The RA field in an lmw instruction, which has special value
> - restrictions. */
> -#define RAM (RAL + 1)
> - { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
> -
> - /* The RA field in a D or X form instruction which is an updating
> - store or an updating floating point load, which means that the RA
> - field may not be zero. */
> -#define RAS (RAM + 1)
> - { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
> -
> - /* The RB field in an X, XO, M, or MDS form instruction. */
> -#define RB (RAS + 1)
> -#define RB_MASK (0x1f << 11)
> - { 5, 11, 0, 0, PPC_OPERAND_GPR },
> -
> - /* The RB field in an X form instruction when it must be the same as
> - the RS field in the instruction. This is used for extended
> - mnemonics like mr. */
> -#define RBS (RB + 1)
> - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
> -
> - /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
> - instruction or the RT field in a D, DS, X, XFX or XO form
> - instruction. */
> -#define RS (RBS + 1)
> -#define RT (RS)
> -#define RT_MASK (0x1f << 21)
> - { 5, 21, 0, 0, PPC_OPERAND_GPR },
> -
> - /* The SH field in an X or M form instruction. */
> -#define SH (RS + 1)
> -#define SH_MASK (0x1f << 11)
> - { 5, 11, 0, 0, 0 },
> -
> - /* The SH field in an MD form instruction. This is split. */
> -#define SH6 (SH + 1)
> -#define SH6_MASK ((0x1f << 11) | (1 << 1))
> - { 6, 1, insert_sh6, extract_sh6, 0 },
> -
> - /* The SI field in a D form instruction. */
> -#define SI (SH6 + 1)
> - { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
> -
> - /* The SI field in a D form instruction when we accept a wide range
> - of positive values. */
> -#define SISIGNOPT (SI + 1)
> - { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
> -
> - /* The SPR field in an XFX form instruction. This is flipped--the
> - lower 5 bits are stored in the upper 5 and vice- versa. */
> -#define SPR (SISIGNOPT + 1)
> -#define SPR_MASK (0x3ff << 11)
> - { 10, 11, insert_spr, extract_spr, 0 },
> -
> - /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
> -#define SPRBAT (SPR + 1)
> -#define SPRBAT_MASK (0x3 << 17)
> - { 2, 17, 0, 0, 0 },
> -
> - /* The SPRG register number in an XFX form m[ft]sprg instruction. */
> -#define SPRG (SPRBAT + 1)
> -#define SPRG_MASK (0x3 << 16)
> - { 2, 16, 0, 0, 0 },
> -
> - /* The SR field in an X form instruction. */
> -#define SR (SPRG + 1)
> - { 4, 16, 0, 0, 0 },
> -
> - /* The SV field in a POWER SC form instruction. */
> -#define SV (SR + 1)
> - { 14, 2, 0, 0, 0 },
> -
> - /* The TBR field in an XFX form instruction. This is like the SPR
> - field, but it is optional. */
> -#define TBR (SV + 1)
> - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
> -
> - /* The TO field in a D or X form instruction. */
> -#define TO (TBR + 1)
> -#define TO_MASK (0x1f << 21)
> - { 5, 21, 0, 0, 0 },
> -
> - /* The U field in an X form instruction. */
> -#define U (TO + 1)
> - { 4, 12, 0, 0, 0 },
> -
> - /* The UI field in a D form instruction. */
> -#define UI (U + 1)
> - { 16, 0, 0, 0, 0 },
> -};
> -
> -/* The functions used to insert and extract complicated operands. */
> -
> -/* The BA field in an XL form instruction when it must be the same as
> - the BT field in the same instruction. This operand is marked FAKE.
> - The insertion function just copies the BT field into the BA field,
> - and the extraction function just checks that the fields are the
> - same. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_bat (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | (((insn >> 21) & 0x1f) << 16);
> -}
> -
> -static long
> -extract_bat (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if (invalid != (int *) NULL
> - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
> - *invalid = 1;
> - return 0;
> -}
> -
> -/* The BB field in an XL form instruction when it must be the same as
> - the BA field in the same instruction. This operand is marked FAKE.
> - The insertion function just copies the BA field into the BB field,
> - and the extraction function just checks that the fields are the
> - same. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_bba (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | (((insn >> 16) & 0x1f) << 11);
> -}
> -
> -static long
> -extract_bba (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if (invalid != (int *) NULL
> - && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
> - *invalid = 1;
> - return 0;
> -}
> -
> -/* The BD field in a B form instruction. The lower two bits are
> - forced to zero. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_bd (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | (value & 0xfffc);
> -}
> -
> -/*ARGSUSED*/
> -static long
> -extract_bd (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if ((insn & 0x8000) != 0)
> - return (insn & 0xfffc) - 0x10000;
> - else
> - return insn & 0xfffc;
> -}
> -
> -/* The BD field in a B form instruction when the - modifier is used.
> - This modifier means that the branch is not expected to be taken.
> - We must set the y bit of the BO field to 1 if the offset is
> - negative. When extracting, we require that the y bit be 1 and that
> - the offset be positive, since if the y bit is 0 we just want to
> - print the normal form of the instruction. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_bdm (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if ((value & 0x8000) != 0)
> - insn |= 1 << 21;
> - return insn | (value & 0xfffc);
> -}
> -
> -static long
> -extract_bdm (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if (invalid != (int *) NULL
> - && ((insn & (1 << 21)) == 0
> - || (insn & (1 << 15)) == 0))
> - *invalid = 1;
> - if ((insn & 0x8000) != 0)
> - return (insn & 0xfffc) - 0x10000;
> - else
> - return insn & 0xfffc;
> -}
> -
> -/* The BD field in a B form instruction when the + modifier is used.
> - This is like BDM, above, except that the branch is expected to be
> - taken. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_bdp (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if ((value & 0x8000) == 0)
> - insn |= 1 << 21;
> - return insn | (value & 0xfffc);
> -}
> -
> -static long
> -extract_bdp (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if (invalid != (int *) NULL
> - && ((insn & (1 << 21)) == 0
> - || (insn & (1 << 15)) != 0))
> - *invalid = 1;
> - if ((insn & 0x8000) != 0)
> - return (insn & 0xfffc) - 0x10000;
> - else
> - return insn & 0xfffc;
> -}
> -
> -/* Check for legal values of a BO field. */
> -
> -static int
> -valid_bo (value)
> - long value;
> -{
> - /* Certain encodings have bits that are required to be zero. These
> - are (z must be zero, y may be anything):
> - 001zy
> - 011zy
> - 1z00y
> - 1z01y
> - 1z1zz
> - */
> - switch (value & 0x14)
> - {
> - default:
> - case 0:
> - return 1;
> - case 0x4:
> - return (value & 0x2) == 0;
> - case 0x10:
> - return (value & 0x8) == 0;
> - case 0x14:
> - return value == 0x14;
> - }
> -}
> -
> -/* The BO field in a B form instruction. Warn about attempts to set
> - the field to an illegal value. */
> -
> -static unsigned long
> -insert_bo (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (errmsg != (const char **) NULL
> - && ! valid_bo (value))
> - *errmsg = "invalid conditional option";
> - return insn | ((value & 0x1f) << 21);
> -}
> -
> -static long
> -extract_bo (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - long value;
> -
> - value = (insn >> 21) & 0x1f;
> - if (invalid != (int *) NULL
> - && ! valid_bo (value))
> - *invalid = 1;
> - return value;
> -}
> -
> -/* The BO field in a B form instruction when the + or - modifier is
> - used. This is like the BO field, but it must be even. When
> - extracting it, we force it to be even. */
> -
> -static unsigned long
> -insert_boe (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (errmsg != (const char **) NULL)
> - {
> - if (! valid_bo (value))
> - *errmsg = "invalid conditional option";
> - else if ((value & 1) != 0)
> - *errmsg = "attempt to set y bit when using + or - modifier";
> - }
> - return insn | ((value & 0x1f) << 21);
> -}
> -
> -static long
> -extract_boe (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - long value;
> -
> - value = (insn >> 21) & 0x1f;
> - if (invalid != (int *) NULL
> - && ! valid_bo (value))
> - *invalid = 1;
> - return value & 0x1e;
> -}
> -
> -/* The DS field in a DS form instruction. This is like D, but the
> - lower two bits are forced to zero. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_ds (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | (value & 0xfffc);
> -}
> -
> -/*ARGSUSED*/
> -static long
> -extract_ds (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if ((insn & 0x8000) != 0)
> - return (insn & 0xfffc) - 0x10000;
> - else
> - return insn & 0xfffc;
> -}
> -
> -/* The LI field in an I form instruction. The lower two bits are
> - forced to zero. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_li (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | (value & 0x3fffffc);
> -}
> -
> -/*ARGSUSED*/
> -static long
> -extract_li (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if ((insn & 0x2000000) != 0)
> - return (insn & 0x3fffffc) - 0x4000000;
> - else
> - return insn & 0x3fffffc;
> -}
> -
> -/* The MB and ME fields in an M form instruction expressed as a single
> - operand which is itself a bitmask. The extraction function always
> - marks it as invalid, since we never want to recognize an
> - instruction which uses a field of this type. */
> -
> -static unsigned long
> -insert_mbe (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - unsigned long uval;
> - int mb, me;
> -
> - uval = value;
> -
> - if (uval == 0)
> - {
> - if (errmsg != (const char **) NULL)
> - *errmsg = "illegal bitmask";
> - return insn;
> - }
> -
> - me = 31;
> - while ((uval & 1) == 0)
> - {
> - uval >>= 1;
> - --me;
> - }
> -
> - mb = me;
> - uval >>= 1;
> - while ((uval & 1) != 0)
> - {
> - uval >>= 1;
> - --mb;
> - }
> -
> - if (uval != 0)
> - {
> - if (errmsg != (const char **) NULL)
> - *errmsg = "illegal bitmask";
> - }
> -
> - return insn | (mb << 6) | (me << 1);
> -}
> -
> -static long
> -extract_mbe (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - long ret;
> - int mb, me;
> - int i;
> -
> - if (invalid != (int *) NULL)
> - *invalid = 1;
> -
> - ret = 0;
> - mb = (insn >> 6) & 0x1f;
> - me = (insn >> 1) & 0x1f;
> - for (i = mb; i < me; i++)
> - ret |= 1 << (31 - i);
> - return ret;
> -}
> -
> -/* The MB or ME field in an MD or MDS form instruction. The high bit
> - is wrapped to the low end. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_mb6 (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | ((value & 0x1f) << 6) | (value & 0x20);
> -}
> -
> -/*ARGSUSED*/
> -static long
> -extract_mb6 (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - return ((insn >> 6) & 0x1f) | (insn & 0x20);
> -}
> -
> -/* The NB field in an X form instruction. The value 32 is stored as
> - 0. */
> -
> -static unsigned long
> -insert_nb (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (value < 0 || value > 32)
> - *errmsg = "value out of range";
> - if (value == 32)
> - value = 0;
> - return insn | ((value & 0x1f) << 11);
> -}
> -
> -/*ARGSUSED*/
> -static long
> -extract_nb (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - long ret;
> -
> - ret = (insn >> 11) & 0x1f;
> - if (ret == 0)
> - ret = 32;
> - return ret;
> -}
> -
> -/* The NSI field in a D form instruction. This is the same as the SI
> - field, only negated. The extraction function always marks it as
> - invalid, since we never want to recognize an instruction which uses
> - a field of this type. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_nsi (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | ((- value) & 0xffff);
> -}
> -
> -static long
> -extract_nsi (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if (invalid != (int *) NULL)
> - *invalid = 1;
> - if ((insn & 0x8000) != 0)
> - return - ((insn & 0xffff) - 0x10000);
> - else
> - return - (insn & 0xffff);
> -}
> -
> -/* The RA field in a D or X form instruction which is an updating
> - load, which means that the RA field may not be zero and may not
> - equal the RT field. */
> -
> -static unsigned long
> -insert_ral (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (value == 0
> - || value == ((insn >> 21) & 0x1f))
> - *errmsg = "invalid register operand when updating";
> - return insn | ((value & 0x1f) << 16);
> -}
> -
> -/* The RA field in an lmw instruction, which has special value
> - restrictions. */
> -
> -static unsigned long
> -insert_ram (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (value >= ((insn >> 21) & 0x1f))
> - *errmsg = "index register in load range";
> - return insn | ((value & 0x1f) << 16);
> -}
> -
> -/* The RA field in a D or X form instruction which is an updating
> - store or an updating floating point load, which means that the RA
> - field may not be zero. */
> -
> -static unsigned long
> -insert_ras (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (value == 0)
> - *errmsg = "invalid register operand when updating";
> - return insn | ((value & 0x1f) << 16);
> -}
> -
> -/* The RB field in an X form instruction when it must be the same as
> - the RS field in the instruction. This is used for extended
> - mnemonics like mr. This operand is marked FAKE. The insertion
> - function just copies the BT field into the BA field, and the
> - extraction function just checks that the fields are the same. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_rbs (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | (((insn >> 21) & 0x1f) << 11);
> -}
> -
> -static long
> -extract_rbs (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - if (invalid != (int *) NULL
> - && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
> - *invalid = 1;
> - return 0;
> -}
> -
> -/* The SH field in an MD form instruction. This is split. */
> -
> -/*ARGSUSED*/
> -static unsigned long
> -insert_sh6 (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
> -}
> -
> -/*ARGSUSED*/
> -static long
> -extract_sh6 (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
> -}
> -
> -/* The SPR field in an XFX form instruction. This is flipped--the
> - lower 5 bits are stored in the upper 5 and vice- versa. */
> -
> -static unsigned long
> -insert_spr (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
> -}
> -
> -static long
> -extract_spr (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
> -}
> -
> -/* The TBR field in an XFX instruction. This is just like SPR, but it
> - is optional. When TBR is omitted, it must be inserted as 268 (the
> - magic number of the TB register). These functions treat 0
> - (indicating an omitted optional operand) as 268. This means that
> - ``mftb 4,0'' is not handled correctly. This does not matter very
> - much, since the architecture manual does not define mftb as
> - accepting any values other than 268 or 269. */
> -
> -#define TB (268)
> -
> -static unsigned long
> -insert_tbr (insn, value, errmsg)
> - unsigned long insn;
> - long value;
> - const char **errmsg;
> -{
> - if (value == 0)
> - value = TB;
> - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
> -}
> -
> -static long
> -extract_tbr (insn, invalid)
> - unsigned long insn;
> - int *invalid;
> -{
> - long ret;
> -
> - ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
> - if (ret == TB)
> - ret = 0;
> - return ret;
> -}
> -
> -/* Macros used to form opcodes. */
> -
> -/* The main opcode. */
> -#define OP(x) (((x) & 0x3f) << 26)
> -#define OP_MASK OP (0x3f)
> -
> -/* The main opcode combined with a trap code in the TO field of a D
> - form instruction. Used for extended mnemonics for the trap
> - instructions. */
> -#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
> -#define OPTO_MASK (OP_MASK | TO_MASK)
> -
> -/* The main opcode combined with a comparison size bit in the L field
> - of a D form or X form instruction. Used for extended mnemonics for
> - the comparison instructions. */
> -#define OPL(x,l) (OP (x) | (((l) & 1) << 21))
> -#define OPL_MASK OPL (0x3f,1)
> -
> -/* An A form instruction. */
> -#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
> -#define A_MASK A (0x3f, 0x1f, 1)
> -
> -/* An A_MASK with the FRB field fixed. */
> -#define AFRB_MASK (A_MASK | FRB_MASK)
> -
> -/* An A_MASK with the FRC field fixed. */
> -#define AFRC_MASK (A_MASK | FRC_MASK)
> -
> -/* An A_MASK with the FRA and FRC fields fixed. */
> -#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
> -
> -/* A B form instruction. */
> -#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
> -#define B_MASK B (0x3f, 1, 1)
> -
> -/* A B form instruction setting the BO field. */
> -#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
> -#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
> -
> -/* A BBO_MASK with the y bit of the BO field removed. This permits
> - matching a conditional branch regardless of the setting of the y
> - bit. */
> -#define Y_MASK (1 << 21)
> -#define BBOY_MASK (BBO_MASK &~ Y_MASK)
> -
> -/* A B form instruction setting the BO field and the condition bits of
> - the BI field. */
> -#define BBOCB(op, bo, cb, aa, lk) \
> - (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
> -#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
> -
> -/* A BBOCB_MASK with the y bit of the BO field removed. */
> -#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
> -
> -/* A BBOYCB_MASK in which the BI field is fixed. */
> -#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
> -
> -/* The main opcode mask with the RA field clear. */
> -#define DRA_MASK (OP_MASK | RA_MASK)
> -
> -/* A DS form instruction. */
> -#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
> -#define DS_MASK DSO (0x3f, 3)
> -
> -/* An M form instruction. */
> -#define M(op, rc) (OP (op) | ((rc) & 1))
> -#define M_MASK M (0x3f, 1)
> -
> -/* An M form instruction with the ME field specified. */
> -#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
> -
> -/* An M_MASK with the MB and ME fields fixed. */
> -#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
> -
> -/* An M_MASK with the SH and ME fields fixed. */
> -#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
> -
> -/* An MD form instruction. */
> -#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
> -#define MD_MASK MD (0x3f, 0x7, 1)
> -
> -/* An MD_MASK with the MB field fixed. */
> -#define MDMB_MASK (MD_MASK | MB6_MASK)
> -
> -/* An MD_MASK with the SH field fixed. */
> -#define MDSH_MASK (MD_MASK | SH6_MASK)
> -
> -/* An MDS form instruction. */
> -#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
> -#define MDS_MASK MDS (0x3f, 0xf, 1)
> -
> -/* An MDS_MASK with the MB field fixed. */
> -#define MDSMB_MASK (MDS_MASK | MB6_MASK)
> -
> -/* An SC form instruction. */
> -#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
> -#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
> -
> -/* An X form instruction. */
> -#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
> -
> -/* An X form instruction with the RC bit specified. */
> -#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
> -
> -/* The mask for an X form instruction. */
> -#define X_MASK XRC (0x3f, 0x3ff, 1)
> -
> -/* An X_MASK with the RA field fixed. */
> -#define XRA_MASK (X_MASK | RA_MASK)
> -
> -/* An X_MASK with the RB field fixed. */
> -#define XRB_MASK (X_MASK | RB_MASK)
> -
> -/* An X_MASK with the RT field fixed. */
> -#define XRT_MASK (X_MASK | RT_MASK)
> -
> -/* An X_MASK with the RA and RB fields fixed. */
> -#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
> -
> -/* An X_MASK with the RT and RA fields fixed. */
> -#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
> -
> -/* An X form comparison instruction. */
> -#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
> -
> -/* The mask for an X form comparison instruction. */
> -#define XCMP_MASK (X_MASK | (1 << 22))
> -
> -/* The mask for an X form comparison instruction with the L field
> - fixed. */
> -#define XCMPL_MASK (XCMP_MASK | (1 << 21))
> -
> -/* An X form trap instruction with the TO field specified. */
> -#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
> -#define XTO_MASK (X_MASK | TO_MASK)
> -
> -/* An XFL form instruction. */
> -#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
> -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
> -
> -/* An XL form instruction with the LK field set to 0. */
> -#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
> -
> -/* An XL form instruction which uses the LK field. */
> -#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
> -
> -/* The mask for an XL form instruction. */
> -#define XL_MASK XLLK (0x3f, 0x3ff, 1)
> -
> -/* An XL form instruction which explicitly sets the BO field. */
> -#define XLO(op, bo, xop, lk) \
> - (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
> -#define XLO_MASK (XL_MASK | BO_MASK)
> -
> -/* An XL form instruction which explicitly sets the y bit of the BO
> - field. */
> -#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
> -#define XLYLK_MASK (XL_MASK | Y_MASK)
> -
> -/* An XL form instruction which sets the BO field and the condition
> - bits of the BI field. */
> -#define XLOCB(op, bo, cb, xop, lk) \
> - (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
> -#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
> -
> -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
> -#define XLBB_MASK (XL_MASK | BB_MASK)
> -#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
> -#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
> -
> -/* An XL_MASK with the BO and BB fields fixed. */
> -#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
> -
> -/* An XL_MASK with the BO, BI and BB fields fixed. */
> -#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
> -
> -/* An XO form instruction. */
> -#define XO(op, xop, oe, rc) \
> - (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
> -#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
> -
> -/* An XO_MASK with the RB field fixed. */
> -#define XORB_MASK (XO_MASK | RB_MASK)
> -
> -/* An XS form instruction. */
> -#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
> -#define XS_MASK XS (0x3f, 0x1ff, 1)
> -
> -/* A mask for the FXM version of an XFX form instruction. */
> -#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
> -
> -/* An XFX form instruction with the FXM field filled in. */
> -#define XFXM(op, xop, fxm) \
> - (X ((op), (xop)) | (((fxm) & 0xff) << 12))
> -
> -/* An XFX form instruction with the SPR field filled in. */
> -#define XSPR(op, xop, spr) \
> - (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
> -#define XSPR_MASK (X_MASK | SPR_MASK)
> -
> -/* An XFX form instruction with the SPR field filled in except for the
> - SPRBAT field. */
> -#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
> -
> -/* An XFX form instruction with the SPR field filled in except for the
> - SPRG field. */
> -#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
> -
> -/* The BO encodings used in extended conditional branch mnemonics. */
> -#define BODNZF (0x0)
> -#define BODNZFP (0x1)
> -#define BODZF (0x2)
> -#define BODZFP (0x3)
> -#define BOF (0x4)
> -#define BOFP (0x5)
> -#define BODNZT (0x8)
> -#define BODNZTP (0x9)
> -#define BODZT (0xa)
> -#define BODZTP (0xb)
> -#define BOT (0xc)
> -#define BOTP (0xd)
> -#define BODNZ (0x10)
> -#define BODNZP (0x11)
> -#define BODZ (0x12)
> -#define BODZP (0x13)
> -#define BOU (0x14)
> -
> -/* The BI condition bit encodings used in extended conditional branch
> - mnemonics. */
> -#define CBLT (0)
> -#define CBGT (1)
> -#define CBEQ (2)
> -#define CBSO (3)
> -
> -/* The TO encodings used in extended trap mnemonics. */
> -#define TOLGT (0x1)
> -#define TOLLT (0x2)
> -#define TOEQ (0x4)
> -#define TOLGE (0x5)
> -#define TOLNL (0x5)
> -#define TOLLE (0x6)
> -#define TOLNG (0x6)
> -#define TOGT (0x8)
> -#define TOGE (0xc)
> -#define TONL (0xc)
> -#define TOLT (0x10)
> -#define TOLE (0x14)
> -#define TONG (0x14)
> -#define TONE (0x18)
> -#define TOU (0x1f)
> -
> -/* Smaller names for the flags so each entry in the opcodes table will
> - fit on a single line. */
> -#undef PPC
> -#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
> -#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
> -#define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
> -#define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
> -#define PPCONLY PPC_OPCODE_PPC
> -#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
> -#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
> -#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
> -#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
> PPC_OPCODE_ANY
> -#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
> PPC_OPCODE_ANY | PPC_OPCODE_32
> -#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
> -#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
> PPC_OPCODE_ANY
> -#define MFDEC1 PPC_OPCODE_POWER
> -#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
> -
> -/* The opcode table.
> -
> - The format of the opcode table is:
> -
> - NAME OPCODE MASK FLAGS { OPERANDS }
> -
> - NAME is the name of the instruction.
> - OPCODE is the instruction opcode.
> - MASK is the opcode mask; this is used to tell the disassembler
> - which bits in the actual opcode must match OPCODE.
> - FLAGS are flags indicated what processors support the instruction.
> - OPERANDS is the list of operands.
> -
> - The disassembler reads the table in order and prints the first
> - instruction which matches, so this table is sorted to put more
> - specific instructions before more general instructions. It is also
> - sorted by major opcode. */
> -
> -const struct powerpc_opcode powerpc_opcodes[] = {
> -{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
> -{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
> -
> -{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
> -{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
> -{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
> -{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
> -
> -{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
> -{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
> -
> -{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
> -{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
> -
> -{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
> -
> -{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI }
> },
> -{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
> -{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
> -{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
> -
> -{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI }
> },
> -{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI }
> },
> -{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
> -{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
> -
> -{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
> -{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI }
> },
> -{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
> -
> -{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
> -{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
> -{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
> -
> -{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
> -{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
> -{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
> -{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
> -{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
> -{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
> -
> -{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
> -{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
> -{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
> -{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
> -{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
> -
> -{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
> -{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
> -{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } },
> -{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } },
> -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
> -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
> -{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } },
> -{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } },
> -{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
> -{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
> -{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } },
> -{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } },
> -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
> -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
> -{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } },
> -{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } },
> -{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
> -{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
> -{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } },
> -{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
> -{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
> -{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } },
> -{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
> -{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
> -{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } },
> -{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
> -{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
> -{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } },
> -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
> -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
> -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
> -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
> -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
> -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
> -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
> -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
> -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
> -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
> -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
> -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
> -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
> -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
> -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
> -{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
> -{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
> -{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
> -{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
> -{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
> -{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
> -{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
> -{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
> -{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
> -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
> -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
> -{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
> -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
> -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
> -{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
> -{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM
> } },
> -{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP
> } },
> -{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD }
> },
> -{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM
> } },
> -{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP
> } },
> -{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD }
> },
> -{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA
> } },
> -{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA
> } },
> -{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA }
> },
> -{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA
> } },
> -{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA
> } },
> -{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA }
> },
> -
> -{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
> -{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
> -{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
> -{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
> -{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
> -
> -{ "b", B(18,0,0), B_MASK, COM, { LI } },
> -{ "bl", B(18,0,1), B_MASK, COM, { LI } },
> -{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
> -{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
> -
> -{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
> -
> -{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
> -{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
> -{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
> -{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
> -{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
> -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
> -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
> -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
> -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
> -{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
> -{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
> -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
> -{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
> -{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
> -{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
> -{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
> -{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
> -{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
> -{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
> -
> -{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
> -{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB }
> },
> -
> -{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
> -{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
> -
> -{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
> -
> -{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
> -{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
> -
> -{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
> -{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
> -{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
> -{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
> -
> -{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
> -{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
> -{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR }
> },
> -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
> -{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
> -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
> -{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
> -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
> -{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
> -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
> -{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
> -{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
> -{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
> -{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
> -{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
> -
> -{ "rlwimi", M(20,0), M_MASK, PPCCOM, {
> RA,RS,SH,MBE,ME } },
> -{ "rlimi", M(20,0), M_MASK, PWRCOM, {
> RA,RS,SH,MBE,ME } },
> -
> -{ "rlwimi.", M(20,1), M_MASK, PPCCOM, {
> RA,RS,SH,MBE,ME } },
> -{ "rlimi.", M(20,1), M_MASK, PWRCOM, {
> RA,RS,SH,MBE,ME } },
> -
> -{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH }
> },
> -{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB }
> },
> -{ "rlwinm", M(21,0), M_MASK, PPCCOM, {
> RA,RS,SH,MBE,ME } },
> -{ "rlinm", M(21,0), M_MASK, PWRCOM, {
> RA,RS,SH,MBE,ME } },
> -{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
> -{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB }
> },
> -{ "rlwinm.", M(21,1), M_MASK, PPCCOM, {
> RA,RS,SH,MBE,ME } },
> -{ "rlinm.", M(21,1), M_MASK, PWRCOM, {
> RA,RS,SH,MBE,ME } },
> -
> -{ "rlmi", M(22,0), M_MASK, M601, {
> RA,RS,RB,MBE,ME } },
> -{ "rlmi.", M(22,1), M_MASK, M601, {
> RA,RS,RB,MBE,ME } },
> -
> -{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB }
> },
> -{ "rlwnm", M(23,0), M_MASK, PPCCOM, {
> RA,RS,RB,MBE,ME } },
> -{ "rlnm", M(23,0), M_MASK, PWRCOM, {
> RA,RS,RB,MBE,ME } },
> -{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB }
> },
> -{ "rlwnm.", M(23,1), M_MASK, PPCCOM, {
> RA,RS,RB,MBE,ME } },
> -{ "rlnm.", M(23,1), M_MASK, PWRCOM, {
> RA,RS,RB,MBE,ME } },
> -
> -{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
> -{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
> -{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
> -
> -{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
> -{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
> -
> -{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
> -{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
> -
> -{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
> -{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
> -
> -{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
> -{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
> -
> -{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
> -{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
> -
> -{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
> -{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
> -{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
> -{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
> -{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
> -{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
> -
> -{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
> -{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
> -
> -{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
> -{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
> -
> -{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
> -{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
> -
> -{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB }
> },
> -{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
> -{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB }
> },
> -{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
> -
> -{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
> -{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
> -
> -{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB }
> },
> -{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB }
> },
> -{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB
> } },
> -{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB }
> },
> -
> -{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
> -{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
> -{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
> -{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB }
> },
> -{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB }
> },
> -
> -{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
> -{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
> -{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
> -{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
> -
> -{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
> -{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
> -
> -{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
> -{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
> -{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
> -
> -{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
> -{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
> -
> -{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
> -
> -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB }
> },
> -
> -{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB }
> },
> -
> -{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
> -{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
> -{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
> -{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
> -
> -{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
> -{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
> -{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
> -{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
> -
> -{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
> -{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
> -
> -{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
> -{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
> -{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
> -{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB }
> },
> -{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB
> } },
> -{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB }
> },
> -
> -{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
> -{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
> -{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
> -{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
> -{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
> -{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
> -{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
> -{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
> -
> -{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB }
> },
> -
> -{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB }
> },
> -{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
> -{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
> -
> -{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
> -{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
> -{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
> -{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB }
> },
> -
> -{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
> -{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
> -
> -{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
> -{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
> -
> -{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
> -
> -{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB }
> },
> -
> -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB }
> },
> -
> -{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
> -{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
> -{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
> -{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
> -
> -{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB }
> },
> -
> -{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
> -
> -{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB }
> },
> -
> -{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
> -{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
> -{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
> -{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
> -{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
> -
> -{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
> -
> -{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB }
> },
> -
> -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
> -
> -{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB }
> },
> -{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB }
> },
> -
> -{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
> -{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
> -{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB }
> },
> -
> -{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB }
> },
> -{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB }
> },
> -
> -{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
> -{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
> -
> -{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
> -
> -{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
> -
> -{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
> -
> -{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
> -
> -{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
> -
> -{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
> -{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
> -{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
> -
> -{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB }
> },
> -
> -{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
> -{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
> -{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
> -
> -{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
> -{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
> -
> -{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB }
> },
> -
> -{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
> -{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
> -
> -{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB }
> },
> -
> -{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
> -{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
> -
> -{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB }
> },
> -
> -{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
> -{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
> -{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
> -
> -{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB }
> },
> -
> -{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB }
> },
> -
> -{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
> -{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
> -
> -{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB }
> },
> -
> -{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
> -{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
> -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
> -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
> -{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
> -{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
> -{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
> -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
> -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
> -{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
> -{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
> -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
> -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
> -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
> -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
> -{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
> -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
> -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
> -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
> -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
> -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
> -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
> -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
> -{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
> -
> -{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB }
> },
> -
> -{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB }
> },
> -
> -{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
> -{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
> -{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
> -{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
> -
> -{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB }
> },
> -{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB }
> },
> -
> -{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
> -
> -{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
> -{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
> -
> -{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB }
> },
> -
> -{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB }
> },
> -
> -{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB }
> },
> -
> -{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB }
> },
> -
> -{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB }
> },
> -
> -{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB }
> },
> -
> -{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB }
> },
> -
> -{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
> -{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
> -{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
> -
> -{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
> -
> -{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB }
> },
> -
> -{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB }
> },
> -
> -{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS }
> },
> -{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
> -{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
> -{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
> -
> -{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB }
> },
> -
> -{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB }
> },
> -{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB }
> },
> -{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB }
> },
> -{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB }
> },
> -
> -{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
> -{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
> -{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
> -{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
> -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
> -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
> -{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
> -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
> -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
> -{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
> -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
> -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
> -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
> -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
> -{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
> -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
> -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
> -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
> -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
> -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
> -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
> -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
> -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
> -{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
> -
> -{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
> -{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
> -
> -{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
> -{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
> -{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
> -{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
> -
> -{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB }
> },
> -{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB }
> },
> -
> -{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB }
> },
> -{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB }
> },
> -{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB }
> },
> -{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB }
> },
> -
> -{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
> -
> -{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
> -
> -{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
> -
> -{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
> -
> -{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB }
> },
> -{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB }
> },
> -
> -{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
> -{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
> -{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
> -{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
> -
> -{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
> -{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
> -{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
> -
> -{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
> -{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
> -
> -{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB
> } },
> -
> -{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
> -
> -{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB }
> },
> -{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB }
> },
> -
> -{ "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } },
> -{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
> -
> -{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB }
> },
> -
> -{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
> -
> -{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB
> } },
> -
> -{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
> -
> -{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB }
> },
> -{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB }
> },
> -
> -{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB }
> },
> -{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB }
> },
> -
> -{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB }
> },
> -
> -{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
> -{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
> -{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB
> } },
> -
> -{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
> -{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
> -
> -{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB }
> },
> -{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB }
> },
> -
> -{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB }
> },
> -
> -{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
> -{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
> -{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB
> } },
> -
> -{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
> -{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
> -
> -{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB }
> },
> -
> -{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
> -{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
> -{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
> -{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
> -
> -{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
> -{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
> -
> -{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB }
> },
> -
> -{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
> -{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
> -{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
> -{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
> -
> -{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
> -
> -{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB }
> },
> -
> -{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
> -{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
> -{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
> -
> -{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
> -{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
> -{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
> -{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
> -
> -{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
> -{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
> -
> -{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
> -{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
> -
> -{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
> -
> -{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB }
> },
> -
> -{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
> -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
> -
> -{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
> -
> -{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
> -{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
> -
> -{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
> -{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
> -
> -{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
> -{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
> -
> -{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
> -
> -{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
> -
> -{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
> -{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
> -
> -{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
> -{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
> -
> -{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
> -
> -{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
> -
> -{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
> -
> -{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
> -
> -{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
> -
> -{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
> -
> -{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
> -
> -{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
> -
> -{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
> -{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
> -
> -{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
> -{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
> -
> -{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
> -
> -{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
> -
> -{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
> -
> -{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
> -
> -{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
> -
> -{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
> -
> -{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
> -
> -{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
> -
> -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
> -
> -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
> -
> -{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA }
> },
> -
> -{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
> -
> -{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
> -
> -{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
> -{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
> -
> -{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
> -{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
> -
> -{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
> -{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
> -
> -{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -
> -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -
> -{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
> -{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
> -
> -{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -
> -{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -
> -{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -
> -{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -
> -{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
> -
> -{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
> -
> -{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA }
> },
> -
> -{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS }
> },
> -
> -{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB
> } },
> -
> -{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
> -{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
> -
> -{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
> -{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
> -{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
> -{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
> -
> -{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
> -{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
> -{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
> -{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
> -
> -{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
> -{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
> -{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
> -{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
> -
> -{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
> -{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
> -{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
> -{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
> -
> -{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
> -{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
> -{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
> -{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
> -
> -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, POWER2, { FRT, FRB } },
> -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, POWER2, { FRT, FRB } },
> -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -
> -{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
> -
> -{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
> -{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
> -{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
> -{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
> -
> -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
> -
> -{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -
> -{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -
> -{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -
> -{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
> -{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
> -
> -{ "fcmpo", X(63,30), X_MASK|(3<<21), COM, { BF, FRA, FRB
> } },
> -
> -{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
> -{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
> -
> -{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
> -{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
> -
> -{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
> -
> -{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
> -{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
> -
> -{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
> -{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
> -
> -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
> -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
> -
> -{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
> -{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
> -
> -{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
> -{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
> -
> -{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
> -{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
> -
> -{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
> -{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
> -
> -{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
> -{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
> -
> -{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
> -{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
> -
> -{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
> -{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
> -
> -};
> -
> -const int powerpc_num_opcodes =
> - sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
> -
> -/* The macro table. This is only used by the assembler. */
> -
> -const struct powerpc_macro powerpc_macros[] = {
> -{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
> -{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
> -{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
> -{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
> -{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
> -{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
> -{ "rotrdi", 3, PPC64, "rldicl %0,%1,64-(%2),0" },
> -{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,64-(%2),0" },
> -{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
> -{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
> -{ "srdi", 3, PPC64, "rldicl %0,%1,64-(%2),%2" },
> -{ "srdi.", 3, PPC64, "rldicl. %0,%1,64-(%2),%2" },
> -{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
> -{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
> -{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
> -{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
> -
> -{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
> -{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
> -{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
> -{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
> -{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
> -{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
> -{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
> -{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
> -{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,32-(%2),0,31" },
> -{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,32-(%2),0,31" },
> -{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
> -{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
> -{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
> -{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
> -{ "srwi", 3, PPCCOM, "rlwinm %0,%1,32-(%2),%2,31" },
> -{ "sri", 3, PWRCOM, "rlinm %0,%1,32-(%2),%2,31" },
> -{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,32-(%2),%2,31" },
> -{ "sri.", 3, PWRCOM, "rlinm. %0,%1,32-(%2),%2,31" },
> -{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
> -{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
> -{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
> -{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
> -
> -};
> -
> -const int powerpc_num_macros =
> - sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
> diff --git a/opcode/ppc.h b/opcode/ppc.h
> deleted file mode 100644
> index c22eb84..0000000
> --- a/opcode/ppc.h
> +++ /dev/null
> @@ -1,248 +0,0 @@
> -/* ppc.h -- Header file for PowerPC opcode table
> - Copyright 1994, 1995 Free Software Foundation, Inc.
> - Written by Ian Lance Taylor, Cygnus Support
> -
> -This file is part of GDB, GAS, and the GNU binutils.
> -
> -GDB, GAS, and the GNU binutils are free software; you can redistribute
> -them and/or modify them under the terms of the GNU General Public
> -License as published by the Free Software Foundation; either version
> -1, or (at your option) any later version.
> -
> -GDB, GAS, and the GNU binutils are distributed in the hope that they
> -will be useful, but WITHOUT ANY WARRANTY; without even the implied
> -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> -the GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this file; see the file COPYING. If not, write to the Free
> -Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -#ifndef PPC_H
> -#define PPC_H
> -
> -/* The opcode table is an array of struct powerpc_opcode. */
> -
> -struct powerpc_opcode
> -{
> - /* The opcode name. */
> - const char *name;
> -
> - /* The opcode itself. Those bits which will be filled in with
> - operands are zeroes. */
> - unsigned long opcode;
> -
> - /* The opcode mask. This is used by the disassembler. This is a
> - mask containing ones indicating those bits which must match the
> - opcode field, and zeroes indicating those bits which need not
> - match (and are presumably filled in by operands). */
> - unsigned long mask;
> -
> - /* One bit flags for the opcode. These are used to indicate which
> - specific processors support the instructions. The defined values
> - are listed below. */
> - unsigned long flags;
> -
> - /* An array of operand codes. Each code is an index into the
> - operand table. They appear in the order which the operands must
> - appear in assembly code, and are terminated by a zero. */
> - unsigned char operands[8];
> -};
> -
> -/* The table itself is sorted by major opcode number, and is otherwise
> - in the order in which the disassembler should consider
> - instructions. */
> -extern const struct powerpc_opcode powerpc_opcodes[];
> -extern const int powerpc_num_opcodes;
> -
> -/* Values defined for the flags field of a struct powerpc_opcode. */
> -
> -/* Opcode is defined for the PowerPC architecture. */
> -#define PPC_OPCODE_PPC (01)
> -
> -/* Opcode is defined for the POWER (RS/6000) architecture. */
> -#define PPC_OPCODE_POWER (02)
> -
> -/* Opcode is defined for the POWER2 (Rios 2) architecture. */
> -#define PPC_OPCODE_POWER2 (04)
> -
> -/* Opcode is only defined on 32 bit architectures. */
> -#define PPC_OPCODE_32 (010)
> -
> -/* Opcode is only defined on 64 bit architectures. */
> -#define PPC_OPCODE_64 (020)
> -
> -/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
> - is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
> - but it also supports many additional POWER instructions. */
> -#define PPC_OPCODE_601 (040)
> -
> -/* Opcode is supported in both the Power and PowerPC architectures
> - (ie, compiler's -mcpu=common or assembler's -mcom). */
> -#define PPC_OPCODE_COMMON (0100)
> -
> -/* Opcode is supported for any Power or PowerPC platform (this is
> - for the assembler's -many option, and it eliminates duplicates). */
> -#define PPC_OPCODE_ANY (0200)
> -
> -/* A macro to extract the major opcode from an instruction. */
> -#define PPC_OP(i) (((i) >> 26) & 0x3f)
> -
> -/* The operands table is an array of struct powerpc_operand. */
> -
> -struct powerpc_operand
> -{
> - /* The number of bits in the operand. */
> - int bits;
> -
> - /* How far the operand is left shifted in the instruction. */
> - int shift;
> -
> - /* Insertion function. This is used by the assembler. To insert an
> - operand value into an instruction, check this field.
> -
> - If it is NULL, execute
> - i |= (op & ((1 << o->bits) - 1)) << o->shift;
> - (i is the instruction which we are filling in, o is a pointer to
> - this structure, and op is the opcode value; this assumes twos
> - complement arithmetic).
> -
> - If this field is not NULL, then simply call it with the
> - instruction and the operand value. It will return the new value
> - of the instruction. If the ERRMSG argument is not NULL, then if
> - the operand value is illegal, *ERRMSG will be set to a warning
> - string (the operand will be inserted in any case). If the
> - operand value is legal, *ERRMSG will be unchanged (most operands
> - can accept any value). */
> - unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
> - const char **errmsg));
> -
> - /* Extraction function. This is used by the disassembler. To
> - extract this operand type from an instruction, check this field.
> -
> - If it is NULL, compute
> - op = ((i) >> o->shift) & ((1 << o->bits) - 1);
> - if ((o->flags & PPC_OPERAND_SIGNED) != 0
> - && (op & (1 << (o->bits - 1))) != 0)
> - op -= 1 << o->bits;
> - (i is the instruction, o is a pointer to this structure, and op
> - is the result; this assumes twos complement arithmetic).
> -
> - If this field is not NULL, then simply call it with the
> - instruction value. It will return the value of the operand. If
> - the INVALID argument is not NULL, *INVALID will be set to
> - non-zero if this operand type can not actually be extracted from
> - this operand (i.e., the instruction does not match). If the
> - operand is valid, *INVALID will not be changed. */
> - long (*extract) PARAMS ((unsigned long instruction, int *invalid));
> -
> - /* One bit syntax flags. */
> - unsigned long flags;
> -};
> -
> -/* Elements in the table are retrieved by indexing with values from
> - the operands field of the powerpc_opcodes table. */
> -
> -extern const struct powerpc_operand powerpc_operands[];
> -
> -/* Values defined for the flags field of a struct powerpc_operand. */
> -
> -/* This operand takes signed values. */
> -#define PPC_OPERAND_SIGNED (01)
> -
> -/* This operand takes signed values, but also accepts a full positive
> - range of values when running in 32 bit mode. That is, if bits is
> - 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
> - this flag is ignored. */
> -#define PPC_OPERAND_SIGNOPT (02)
> -
> -/* This operand does not actually exist in the assembler input. This
> - is used to support extended mnemonics such as mr, for which two
> - operands fields are identical. The assembler should call the
> - insert function with any op value. The disassembler should call
> - the extract function, ignore the return value, and check the value
> - placed in the valid argument. */
> -#define PPC_OPERAND_FAKE (04)
> -
> -/* The next operand should be wrapped in parentheses rather than
> - separated from this one by a comma. This is used for the load and
> - store instructions which want their operands to look like
> - reg,displacement(reg)
> - */
> -#define PPC_OPERAND_PARENS (010)
> -
> -/* This operand may use the symbolic names for the CR fields, which
> - are
> - lt 0 gt 1 eq 2 so 3 un 3
> - cr0 0 cr1 1 cr2 2 cr3 3
> - cr4 4 cr5 5 cr6 6 cr7 7
> - These may be combined arithmetically, as in cr2*4+gt. These are
> - only supported on the PowerPC, not the POWER. */
> -#define PPC_OPERAND_CR (020)
> -
> -/* This operand names a register. The disassembler uses this to print
> - register names with a leading 'r'. */
> -#define PPC_OPERAND_GPR (040)
> -
> -/* This operand names a floating point register. The disassembler
> - prints these with a leading 'f'. */
> -#define PPC_OPERAND_FPR (0100)
> -
> -/* This operand is a relative branch displacement. The disassembler
> - prints these symbolically if possible. */
> -#define PPC_OPERAND_RELATIVE (0200)
> -
> -/* This operand is an absolute branch address. The disassembler
> - prints these symbolically if possible. */
> -#define PPC_OPERAND_ABSOLUTE (0400)
> -
> -/* This operand is optional, and is zero if omitted. This is used for
> - the optional BF and L fields in the comparison instructions. The
> - assembler must count the number of operands remaining on the line,
> - and the number of operands remaining for the opcode, and decide
> - whether this operand is present or not. The disassembler should
> - print this operand out only if it is not zero. */
> -#define PPC_OPERAND_OPTIONAL (01000)
> -
> -/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
> - is omitted, then for the next operand use this operand value plus
> - 1, ignoring the next operand field for the opcode. This wretched
> - hack is needed because the Power rotate instructions can take
> - either 4 or 5 operands. The disassembler should print this operand
> - out regardless of the PPC_OPERAND_OPTIONAL field. */
> -#define PPC_OPERAND_NEXT (02000)
> -
> -/* This operand should be regarded as a negative number for the
> - purposes of overflow checking (i.e., the normal most negative
> - number is disallowed and one more than the normal most positive
> - number is allowed). This flag will only be set for a signed
> - operand. */
> -#define PPC_OPERAND_NEGATIVE (04000)
> -
> -/* The POWER and PowerPC assemblers use a few macros. We keep them
> - with the operands table for simplicity. The macro table is an
> - array of struct powerpc_macro. */
> -
> -struct powerpc_macro
> -{
> - /* The macro name. */
> - const char *name;
> -
> - /* The number of operands the macro takes. */
> - unsigned int operands;
> -
> - /* One bit flags for the opcode. These are used to indicate which
> - specific processors support the instructions. The values are the
> - same as those for the struct powerpc_opcode flags field. */
> - unsigned long flags;
> -
> - /* A format string to turn the macro into a normal instruction.
> - Each %N in the string is replaced with operand number N (zero
> - based). */
> - const char *format;
> -};
> -
> -extern const struct powerpc_macro powerpc_macros[];
> -extern const int powerpc_num_macros;
> -
> -#endif /* PPC_H */
> diff --git a/opcode/sparc-dis.c b/opcode/sparc-dis.c
> deleted file mode 100644
> index 23216be..0000000
> --- a/opcode/sparc-dis.c
> +++ /dev/null
> @@ -1,868 +0,0 @@
> -/* Print SPARC instructions.
> - Copyright (C) 1989, 91-93, 1995, 1996 Free Software Foundation, Inc.
> -
> -This program is free software; you can redistribute it and/or modify
> -it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 2 of the License, or
> -(at your option) any later version.
> -
> -This program is distributed in the hope that it will be useful,
> -but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this program; if not, write to the Free Software
> -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA. */
> -
> -#include "ansidecl.h"
> -#include "opcode/sparc.h"
> -#include "dis-asm.h"
> -
> -#include <string.h>
> -
> -/* Bitmask of v9 architectures. */
> -#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
> - | (1 << SPARC_OPCODE_ARCH_V9A))
> -/* 1 if INSN is for v9 only. */
> -#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
> -/* 1 if INSN is for v9. */
> -#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
> -
> -/* For faster lookup, after insns are sorted they are hashed. */
> -/* ??? I think there is room for even more improvement. */
> -
> -#define HASH_SIZE 256
> -/* It is important that we only look at insn code bits as that is how the
> - opcode table is hashed. OPCODE_BITS is a table of valid bits for each
> - of the main types (0,1,2,3). */
> -static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
> -#define HASH_INSN(INSN) \
> - ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >>
> 19))
> -struct opcode_hash {
> - struct opcode_hash *next;
> - struct sparc_opcode *opcode;
> -};
> -static struct opcode_hash *opcode_hash_table[HASH_SIZE];
> -static void build_hash_table ();
> -
> -/* Sign-extend a value which is N bits long. */
> -#define SEX(value, bits) \
> - ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
> - >> ((8 * sizeof (int)) - bits) )
> -
> -static char *reg_names[] =
> -{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
> - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
> - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
> - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
> - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
> - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
> - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
> - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
> - "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
> - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
> - "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
> - "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
> -/* psr, wim, tbr, fpsr, cpsr are v8 only. */
> - "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
> -};
> -
> -#define freg_names (®_names[4 * 8])
> -
> -/* These are ordered according to there register number in
> - rdpr and wrpr insns. */
> -static char *v9_priv_reg_names[] =
> -{
> - "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
> - "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
> - "wstate", "fq"
> - /* "ver" - special cased */
> -};
> -
> -/* Macros used to extract instruction fields. Not all fields have
> - macros defined here, only those which are actually used. */
> -
> -#define X_RD(i) (((i) >> 25) & 0x1f)
> -#define X_RS1(i) (((i) >> 14) & 0x1f)
> -#define X_LDST_I(i) (((i) >> 13) & 1)
> -#define X_ASI(i) (((i) >> 5) & 0xff)
> -#define X_RS2(i) (((i) >> 0) & 0x1f)
> -#define X_IMM13(i) (((i) >> 0) & 0x1fff)
> -#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
> -#define X_IMM22(i) X_DISP22 (i)
> -#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
> -
> -/* These are for v9. */
> -#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
> -#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
> -#define X_MEMBAR(i) ((i) & 0x7f)
> -
> -/* Here is the union which was used to extract instruction fields
> - before the shift and mask macros were written.
> -
> - union sparc_insn
> - {
> - unsigned long int code;
> - struct
> - {
> - unsigned int anop:2;
> - #define op ldst.anop
> - unsigned int anrd:5;
> - #define rd ldst.anrd
> - unsigned int op3:6;
> - unsigned int anrs1:5;
> - #define rs1 ldst.anrs1
> - unsigned int i:1;
> - unsigned int anasi:8;
> - #define asi ldst.anasi
> - unsigned int anrs2:5;
> - #define rs2 ldst.anrs2
> - #define shcnt rs2
> - } ldst;
> - struct
> - {
> - unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
> - unsigned int IMM13:13;
> - #define imm13 IMM13.IMM13
> - } IMM13;
> - struct
> - {
> - unsigned int anop:2;
> - unsigned int a:1;
> - unsigned int cond:4;
> - unsigned int op2:3;
> - unsigned int DISP22:22;
> - #define disp22 branch.DISP22
> - #define imm22 disp22
> - } branch;
> - struct
> - {
> - unsigned int anop:2;
> - unsigned int a:1;
> - unsigned int z:1;
> - unsigned int rcond:3;
> - unsigned int op2:3;
> - unsigned int DISP16HI:2;
> - unsigned int p:1;
> - unsigned int _rs1:5;
> - unsigned int DISP16LO:14;
> - } branch16;
> - struct
> - {
> - unsigned int anop:2;
> - unsigned int adisp30:30;
> - #define disp30 call.adisp30
> - } call;
> - };
> -
> - */
> -
> -/* Nonzero if INSN is the opcode for a delayed branch. */
> -static int
> -is_delayed_branch (insn)
> - unsigned long insn;
> -{
> - struct opcode_hash *op;
> -
> - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
> - {
> - const struct sparc_opcode *opcode = op->opcode;
> - if ((opcode->match & insn) == opcode->match
> - && (opcode->lose & insn) == 0)
> - return (opcode->flags & F_DELAYED);
> - }
> - return 0;
> -}
> -
> -/* Nonzero of opcode table has been initialized. */
> -static int opcodes_initialized = 0;
> -
> -/* extern void qsort (); */
> -static int compare_opcodes ();
> -
> -/* Print one instruction from MEMADDR on INFO->STREAM.
> -
> - We suffix the instruction with a comment that gives the absolute
> - address involved, as well as its symbolic form, if the instruction
> - is preceded by a findable `sethi' and it either adds an immediate
> - displacement to that register, or it is an `add' or `or' instruction
> - on that register. */
> -
> -int
> -print_insn_sparc (memaddr, info)
> - bfd_vma memaddr;
> - disassemble_info *info;
> -{
> - FILE *stream = info->stream;
> - bfd_byte buffer[4];
> - unsigned long insn;
> - register unsigned int i;
> - register struct opcode_hash *op;
> - int sparc_v9_p = bfd_mach_sparc_v9_p (info->mach);
> -
> - if (!opcodes_initialized)
> - {
> - qsort ((char *) sparc_opcodes, sparc_num_opcodes,
> - sizeof (sparc_opcodes[0]), compare_opcodes);
> - build_hash_table (sparc_opcodes, opcode_hash_table, sparc_num_opcodes);
> - opcodes_initialized = 1;
> - }
> -
> - {
> - int status =
> - (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
> - if (status != 0)
> - {
> - (*info->memory_error_func) (status, memaddr, info);
> - return -1;
> - }
> - }
> -
> - insn = bfd_getb32 (buffer);
> -
> - info->insn_info_valid = 1; /* We do return this info */
> - info->insn_type = dis_nonbranch; /* Assume non branch insn */
> - info->branch_delay_insns = 0; /* Assume no delay */
> - info->target = 0; /* Assume no target known */
> -
> - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
> - {
> - const struct sparc_opcode *opcode = op->opcode;
> -
> - /* ??? These architecture tests need to be more selective. */
> -
> - /* If the current architecture isn't sparc64, skip sparc64 insns. */
> - if (!sparc_v9_p
> - && V9_ONLY_P (opcode))
> - continue;
> -
> - /* If the current architecture is sparc64, skip sparc32 only insns. */
> - if (sparc_v9_p
> - && ! V9_P (opcode))
> - continue;
> -
> - if ((opcode->match & insn) == opcode->match
> - && (opcode->lose & insn) == 0)
> - {
> - /* Nonzero means that we have found an instruction which has
> - the effect of adding or or'ing the imm13 field to rs1. */
> - int imm_added_to_rs1 = 0;
> -
> - /* Nonzero means that we have found a plus sign in the args
> - field of the opcode table. */
> - int found_plus = 0;
> -
> - /* Nonzero means we have an annulled branch. */
> - int is_annulled = 0;
> -
> - /* Do we have an `add' or `or' instruction where rs1 is the same
> - as rsd, and which has the i bit set? */
> - if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
> - /* (or) (add) */
> - && X_RS1 (insn) == X_RD (insn))
> - imm_added_to_rs1 = 1;
> -
> - if (X_RS1 (insn) != X_RD (insn)
> - && strchr (opcode->args, 'r') != 0)
> - /* Can't do simple format if source and dest are different. */
> - continue;
> - if (X_RS2 (insn) != X_RD (insn)
> - && strchr (opcode->args, 'O') != 0)
> - /* Can't do simple format if source and dest are different. */
> - continue;
> -
> - (*info->fprintf_func) (stream, opcode->name);
> -
> - {
> - register const char *s;
> -
> - if (opcode->args[0] != ',')
> - (*info->fprintf_func) (stream, " ");
> - for (s = opcode->args; *s != '\0'; ++s)
> - {
> - while (*s == ',')
> - {
> - (*info->fprintf_func) (stream, ",");
> - ++s;
> - switch (*s) {
> - case 'a':
> - (*info->fprintf_func) (stream, "a");
> - is_annulled = 1;
> - ++s;
> - continue;
> - case 'N':
> - (*info->fprintf_func) (stream, "pn");
> - ++s;
> - continue;
> -
> - case 'T':
> - (*info->fprintf_func) (stream, "pt");
> - ++s;
> - continue;
> -
> - default:
> - break;
> - } /* switch on arg */
> - } /* while there are comma started args */
> -
> - (*info->fprintf_func) (stream, " ");
> -
> - switch (*s)
> - {
> - case '+':
> - found_plus = 1;
> -
> - /* note fall-through */
> - default:
> - (*info->fprintf_func) (stream, "%c", *s);
> - break;
> -
> - case '#':
> - (*info->fprintf_func) (stream, "0");
> - break;
> -
> -#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
> - case '1':
> - case 'r':
> - reg (X_RS1 (insn));
> - break;
> -
> - case '2':
> - case 'O':
> - reg (X_RS2 (insn));
> - break;
> -
> - case 'd':
> - reg (X_RD (insn));
> - break;
> -#undef reg
> -
> -#define freg(n) (*info->fprintf_func) (stream, "%%%s",
> freg_names[n])
> -#define fregx(n) (*info->fprintf_func) (stream, "%%%s",
> freg_names[((n) & ~1) | (((n) & 1) << 5)])
> - case 'e':
> - freg (X_RS1 (insn));
> - break;
> - case 'v': /* double/even */
> - case 'V': /* quad/multiple of 4 */
> - fregx (X_RS1 (insn));
> - break;
> -
> - case 'f':
> - freg (X_RS2 (insn));
> - break;
> - case 'B': /* double/even */
> - case 'R': /* quad/multiple of 4 */
> - fregx (X_RS2 (insn));
> - break;
> -
> - case 'g':
> - freg (X_RD (insn));
> - break;
> - case 'H': /* double/even */
> - case 'J': /* quad/multiple of 4 */
> - fregx (X_RD (insn));
> - break;
> -#undef freg
> -#undef fregx
> -
> -#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int)
> (n))
> - case 'b':
> - creg (X_RS1 (insn));
> - break;
> -
> - case 'c':
> - creg (X_RS2 (insn));
> - break;
> -
> - case 'D':
> - creg (X_RD (insn));
> - break;
> -#undef creg
> -
> - case 'h':
> - (*info->fprintf_func) (stream, "%%hi(%#x)",
> - (0xFFFFFFFF
> - & ((int) X_IMM22 (insn) << 10)));
> - break;
> -
> - case 'i':
> - {
> - int imm = SEX (X_IMM13 (insn), 13);
> -
> - /* Check to see whether we have a 1+i, and take
> - note of that fact.
> -
> - Note: because of the way we sort the table,
> - we will be matching 1+i rather than i+1,
> - so it is OK to assume that i is after +,
> - not before it. */
> - if (found_plus)
> - imm_added_to_rs1 = 1;
> -
> - if (imm <= 9)
> - (*info->fprintf_func) (stream, "%d", imm);
> - else
> - (*info->fprintf_func) (stream, "%#x", imm);
> - }
> - break;
> -
> - case 'I': /* 11 bit immediate. */
> - case 'j': /* 10 bit immediate. */
> - {
> - int imm;
> -
> - if (*s == 'I')
> - imm = SEX (X_IMM13 (insn), 11);
> - else
> - imm = SEX (X_IMM13 (insn), 10);
> -
> - /* Check to see whether we have a 1+i, and take
> - note of that fact.
> -
> - Note: because of the way we sort the table,
> - we will be matching 1+i rather than i+1,
> - so it is OK to assume that i is after +,
> - not before it. */
> - if (found_plus)
> - imm_added_to_rs1 = 1;
> -
> - if (imm <= 9)
> - (info->fprintf_func) (stream, "%d", imm);
> - else
> - (info->fprintf_func) (stream, "%#x", (unsigned) imm);
> - }
> - break;
> -
> - case 'K':
> - {
> - int mask = X_MEMBAR (insn);
> - int bit = 0x40, printed_one = 0;
> - char *name;
> -
> - if (mask == 0)
> - (info->fprintf_func) (stream, "0");
> - else
> - while (bit)
> - {
> - if (mask & bit)
> - {
> - if (printed_one)
> - (info->fprintf_func) (stream, "|");
> - name = sparc_decode_membar (bit);
> - (info->fprintf_func) (stream, "%s", name);
> - printed_one = 1;
> - }
> - bit >>= 1;
> - }
> - break;
> - }
> -
> - case 'k':
> - info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
> - (*info->print_address_func) (info->target, info);
> - break;
> -
> - case 'G':
> - info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
> - (*info->print_address_func) (info->target, info);
> - break;
> -
> - case '6':
> - case '7':
> - case '8':
> - case '9':
> - (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
> - break;
> -
> - case 'z':
> - (*info->fprintf_func) (stream, "%%icc");
> - break;
> -
> - case 'Z':
> - (*info->fprintf_func) (stream, "%%xcc");
> - break;
> -
> - case 'E':
> - (*info->fprintf_func) (stream, "%%ccr");
> - break;
> -
> - case 's':
> - (*info->fprintf_func) (stream, "%%fprs");
> - break;
> -
> - case 'o':
> - (*info->fprintf_func) (stream, "%%asi");
> - break;
> -
> - case 'W':
> - (*info->fprintf_func) (stream, "%%tick");
> - break;
> -
> - case 'P':
> - (*info->fprintf_func) (stream, "%%pc");
> - break;
> -
> - case '?':
> - if (X_RS1 (insn) == 31)
> - (*info->fprintf_func) (stream, "%%ver");
> - else if ((unsigned) X_RS1 (insn) < 16)
> - (*info->fprintf_func) (stream, "%%%s",
> - v9_priv_reg_names[X_RS1 (insn)]);
> - else
> - (*info->fprintf_func) (stream, "%%reserved");
> - break;
> -
> - case '!':
> - if ((unsigned) X_RD (insn) < 15)
> - (*info->fprintf_func) (stream, "%%%s",
> - v9_priv_reg_names[X_RD (insn)]);
> - else
> - (*info->fprintf_func) (stream, "%%reserved");
> - break;
> -
> - case '*':
> - {
> - char *name = sparc_decode_prefetch (X_RD (insn));
> -
> - if (name)
> - (*info->fprintf_func) (stream, "%s", name);
> - else
> - (*info->fprintf_func) (stream, "%d", X_RD (insn));
> - break;
> - }
> -
> - case 'M':
> - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
> - break;
> -
> - case 'm':
> - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
> - break;
> -
> - case 'L':
> - info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
> - (*info->print_address_func) (info->target, info);
> - break;
> -
> - case 'n':
> - (*info->fprintf_func)
> - (stream, "%#x", SEX (X_DISP22 (insn), 22));
> - break;
> -
> - case 'l':
> - info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
> - (*info->print_address_func) (info->target, info);
> - break;
> -
> - case 'A':
> - {
> - char *name = sparc_decode_asi (X_ASI (insn));
> -
> - if (name)
> - (*info->fprintf_func) (stream, "%s", name);
> - else
> - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
> - break;
> - }
> -
> - case 'C':
> - (*info->fprintf_func) (stream, "%%csr");
> - break;
> -
> - case 'F':
> - (*info->fprintf_func) (stream, "%%fsr");
> - break;
> -
> - case 'p':
> - (*info->fprintf_func) (stream, "%%psr");
> - break;
> -
> - case 'q':
> - (*info->fprintf_func) (stream, "%%fq");
> - break;
> -
> - case 'Q':
> - (*info->fprintf_func) (stream, "%%cq");
> - break;
> -
> - case 't':
> - (*info->fprintf_func) (stream, "%%tbr");
> - break;
> -
> - case 'w':
> - (*info->fprintf_func) (stream, "%%wim");
> - break;
> -
> - case 'x':
> - (*info->fprintf_func) (stream, "%d",
> - ((X_LDST_I (insn) << 8)
> - + X_ASI (insn)));
> - break;
> -
> - case 'y':
> - (*info->fprintf_func) (stream, "%%y");
> - break;
> -
> - case 'u':
> - case 'U':
> - {
> - int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
> - char *name = sparc_decode_sparclet_cpreg (val);
> -
> - if (name)
> - (*info->fprintf_func) (stream, "%s", name);
> - else
> - (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
> - break;
> - }
> - }
> - }
> - }
> -
> - /* If we are adding or or'ing something to rs1, then
> - check to see whether the previous instruction was
> - a sethi to the same register as in the sethi.
> - If so, attempt to print the result of the add or
> - or (in this context add and or do the same thing)
> - and its symbolic value. */
> - if (imm_added_to_rs1)
> - {
> - unsigned long prev_insn;
> - int errcode;
> -
> - errcode =
> - (*info->read_memory_func)
> - (memaddr - 4, buffer, sizeof (buffer), info);
> - prev_insn = bfd_getb32 (buffer);
> -
> - if (errcode == 0)
> - {
> - /* If it is a delayed branch, we need to look at the
> - instruction before the delayed branch. This handles
> - sequences such as
> -
> - sethi %o1, %hi(_foo), %o1
> - call _printf
> - or %o1, %lo(_foo), %o1
> - */
> -
> - if (is_delayed_branch (prev_insn))
> - {
> - errcode = (*info->read_memory_func)
> - (memaddr - 8, buffer, sizeof (buffer), info);
> - prev_insn = bfd_getb32 (buffer);
> - }
> - }
> -
> - /* If there was a problem reading memory, then assume
> - the previous instruction was not sethi. */
> - if (errcode == 0)
> - {
> - /* Is it sethi to the same register? */
> - if ((prev_insn & 0xc1c00000) == 0x01000000
> - && X_RD (prev_insn) == X_RS1 (insn))
> - {
> - (*info->fprintf_func) (stream, "\t! ");
> - info->target =
> - (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
> - | SEX (X_IMM13 (insn), 13);
> - (*info->print_address_func) (info->target, info);
> - info->insn_type = dis_dref;
> - info->data_size = 4; /* FIXME!!! */
> - }
> - }
> - }
> -
> - if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
> - {
> - /* FIXME -- check is_annulled flag */
> - if (opcode->flags & F_UNBR)
> - info->insn_type = dis_branch;
> - if (opcode->flags & F_CONDBR)
> - info->insn_type = dis_condbranch;
> - if (opcode->flags & F_JSR)
> - info->insn_type = dis_jsr;
> - if (opcode->flags & F_DELAYED)
> - info->branch_delay_insns = 1;
> - }
> -
> - return sizeof (buffer);
> - }
> - }
> -
> - info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
> - (*info->fprintf_func) (stream, "unknown");
> - return sizeof (buffer);
> -}
> -
> -/* Compare opcodes A and B. */
> -
> -static int
> -compare_opcodes (a, b)
> - char *a, *b;
> -{
> - struct sparc_opcode *op0 = (struct sparc_opcode *) a;
> - struct sparc_opcode *op1 = (struct sparc_opcode *) b;
> - unsigned long int match0 = op0->match, match1 = op1->match;
> - unsigned long int lose0 = op0->lose, lose1 = op1->lose;
> - register unsigned int i;
> -
> - /* If a bit is set in both match and lose, there is something
> - wrong with the opcode table. */
> - if (match0 & lose0)
> - {
> - fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx,
> %#.8lx\n",
> - op0->name, match0, lose0);
> - op0->lose &= ~op0->match;
> - lose0 = op0->lose;
> - }
> -
> - if (match1 & lose1)
> - {
> - fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx,
> %#.8lx\n",
> - op1->name, match1, lose1);
> - op1->lose &= ~op1->match;
> - lose1 = op1->lose;
> - }
> -
> - /* Because the bits that are variable in one opcode are constant in
> - another, it is important to order the opcodes in the right order. */
> - for (i = 0; i < 32; ++i)
> - {
> - unsigned long int x = 1 << i;
> - int x0 = (match0 & x) != 0;
> - int x1 = (match1 & x) != 0;
> -
> - if (x0 != x1)
> - return x1 - x0;
> - }
> -
> - for (i = 0; i < 32; ++i)
> - {
> - unsigned long int x = 1 << i;
> - int x0 = (lose0 & x) != 0;
> - int x1 = (lose1 & x) != 0;
> -
> - if (x0 != x1)
> - return x1 - x0;
> - }
> -
> - /* Put non-sparc64 insns ahead of sparc64 ones. */
> - if (V9_ONLY_P (op0) != V9_ONLY_P (op1))
> - return V9_ONLY_P (op0) - V9_ONLY_P (op1);
> -
> - /* They are functionally equal. So as long as the opcode table is
> - valid, we can put whichever one first we want, on aesthetic grounds. */
> -
> - /* Our first aesthetic ground is that aliases defer to real insns. */
> - {
> - int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
> - if (alias_diff != 0)
> - /* Put the one that isn't an alias first. */
> - return alias_diff;
> - }
> -
> - /* Except for aliases, two "identical" instructions had
> - better have the same opcode. This is a sanity check on the table. */
> - i = strcmp (op0->name, op1->name);
> - if (i)
> - if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
> - return i;
> - else
> - fprintf (stderr,
> - "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
> - op0->name, op1->name);
> -
> - /* Fewer arguments are preferred. */
> - {
> - int length_diff = strlen (op0->args) - strlen (op1->args);
> - if (length_diff != 0)
> - /* Put the one with fewer arguments first. */
> - return length_diff;
> - }
> -
> - /* Put 1+i before i+1. */
> - {
> - char *p0 = (char *) strchr(op0->args, '+');
> - char *p1 = (char *) strchr(op1->args, '+');
> -
> - if (p0 && p1)
> - {
> - /* There is a plus in both operands. Note that a plus
> - sign cannot be the first character in args,
> - so the following [-1]'s are valid. */
> - if (p0[-1] == 'i' && p1[1] == 'i')
> - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
> - return 1;
> - if (p0[1] == 'i' && p1[-1] == 'i')
> - /* op0 is 1+i and op1 is i+1, so op0 goes first. */
> - return -1;
> - }
> - }
> -
> - /* Put 1,i before i,1. */
> - {
> - int i0 = strncmp (op0->args, "i,1", 3) == 0;
> - int i1 = strncmp (op1->args, "i,1", 3) == 0;
> -
> - if (i0 ^ i1)
> - return i0 - i1;
> - }
> -
> - /* They are, as far as we can tell, identical.
> - Since qsort may have rearranged the table partially, there is
> - no way to tell which one was first in the opcode table as
> - written, so just say there are equal. */
> - return 0;
> -}
> -
> -/* Build a hash table from the opcode table. */
> -
> -static void
> -build_hash_table (table, hash_table, num_opcodes)
> - struct sparc_opcode *table;
> - struct opcode_hash **hash_table;
> - int num_opcodes;
> -{
> - register int i;
> - int hash_count[HASH_SIZE];
> - static struct opcode_hash *hash_buf = NULL;
> -
> - /* Start at the end of the table and work backwards so that each
> - chain is sorted. */
> -
> - memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
> - memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
> - if (hash_buf != NULL)
> - free (hash_buf);
> - hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) *
> num_opcodes);
> - for (i = num_opcodes - 1; i >= 0; --i)
> - {
> - register int hash = HASH_INSN (sparc_opcodes[i].match);
> - register struct opcode_hash *h = &hash_buf[i];
> - h->next = hash_table[hash];
> - h->opcode = &sparc_opcodes[i];
> - hash_table[hash] = h;
> - ++hash_count[hash];
> - }
> -
> -#if 0 /* for debugging */
> - {
> - int min_count = num_opcodes, max_count = 0;
> - int total;
> -
> - for (i = 0; i < HASH_SIZE; ++i)
> - {
> - if (hash_count[i] < min_count)
> - min_count = hash_count[i];
> - if (hash_count[i] > max_count)
> - max_count = hash_count[i];
> - total += hash_count[i];
> - }
> -
> - printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
> - min_count, max_count, (double) total / HASH_SIZE);
> - }
> -#endif
> -}
> diff --git a/opcode/sparc-opc.c b/opcode/sparc-opc.c
> deleted file mode 100644
> index d21835c..0000000
> --- a/opcode/sparc-opc.c
> +++ /dev/null
> @@ -1,1757 +0,0 @@
> -/* Table of opcodes for the sparc.
> - Copyright (C) 1989, 1991, 1992, 1995, 1996 Free Software Foundation, Inc.
> -
> -This file is part of the BFD library.
> -
> -BFD is free software; you can redistribute it and/or modify it under
> -the terms of the GNU General Public License as published by the Free
> -Software Foundation; either version 2, or (at your option) any later
> -version.
> -
> -BFD is distributed in the hope that it will be useful, but WITHOUT ANY
> -WARRANTY; without even the implied warranty of MERCHANTABILITY or
> -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> -for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with this software; see the file COPYING. If not, write to
> -the Free Software Foundation, 51 Franklin Street, Fifth Floor,
> -Boston, MA 02110-1301, USA. */
> -
> -/* FIXME-someday: perhaps the ,a's and such should be embedded in the
> - instruction's name rather than the args. This would make gas faster,
> pinsn
> - slower, but would mess up some macros a bit. xoxorich. */
> -
> -/* v9 FIXME: Doesn't accept `setsw', `setx' synthetic instructions for v9.
> */
> -
> -#include <stdio.h>
> -#include "ansidecl.h"
> -#include "opcode/sparc.h"
> -
> -/* Some defines to make life easy. */
> -#define MASK_V6 (1 << SPARC_OPCODE_ARCH_V6)
> -#define MASK_V7 (1 << SPARC_OPCODE_ARCH_V7)
> -#define MASK_V8 (1 << SPARC_OPCODE_ARCH_V8)
> -#define MASK_SPARCLET (1 << SPARC_OPCODE_ARCH_SPARCLET)
> -#define MASK_SPARCLITE (1 << SPARC_OPCODE_ARCH_SPARCLITE)
> -#define MASK_V9 (1 << SPARC_OPCODE_ARCH_V9)
> -#define MASK_V9A (1 << SPARC_OPCODE_ARCH_V9A)
> -
> -/* Bit masks of architectures supporting the insn. */
> -
> -#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
> - | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
> -#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
> - | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
> -/* Although not all insns are implemented in hardware, sparclite is defined
> - to be a superset of v8. Unimplemented insns trap and are then
> theoretically
> - implemented in software.
> - It's not clear that the same is true for sparclet, although the docs
> - suggest it is. Rather than complicating things, the sparclet assembler
> - recognizes all v8 insns. */
> -#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE | MASK_V9 |
> MASK_V9A)
> -#define sparclet (MASK_SPARCLET)
> -#define sparclite (MASK_SPARCLITE)
> -#define v9 (MASK_V9 | MASK_V9A)
> -#define v9a (MASK_V9A)
> -/* v6 insns not supported by v9 */
> -#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
> - | MASK_SPARCLET | MASK_SPARCLITE)
> -
> -/* Table of opcode architectures.
> - The order is defined in opcode/sparc.h. */
> -const struct sparc_opcode_arch sparc_opcode_archs[] = {
> - { "v6", MASK_V6 },
> - { "v7", MASK_V6 | MASK_V7 },
> - { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
> - { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
> - { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
> - /* ??? Don't some v8 priviledged insns conflict with v9? */
> - { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
> - /* v9 with ultrasparc additions */
> - { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
> - { NULL, 0 }
> -};
> -
> -/* Given NAME, return it's architecture entry. */
> -
> -enum sparc_opcode_arch_val
> -sparc_opcode_lookup_arch (name)
> - const char *name;
> -{
> - const struct sparc_opcode_arch *p;
> -
> - for (p = &sparc_opcode_archs[0]; p->name; ++p)
> - {
> - if (strcmp (name, p->name) == 0)
> - return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
> - }
> -
> - return SPARC_OPCODE_ARCH_BAD;
> -}
> -
> -/* Branch condition field. */
> -#define COND(x) (((x)&0xf)<<25)
> -
> -/* v9: Move (MOVcc and FMOVcc) condition field. */
> -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /*
> v9 */
> -
> -/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
> -#define RCOND(x) (((x)&0x7)<<10) /* v9 */
> -
> -#define CONDA (COND(0x8))
> -#define CONDCC (COND(0xd))
> -#define CONDCS (COND(0x5))
> -#define CONDE (COND(0x1))
> -#define CONDG (COND(0xa))
> -#define CONDGE (COND(0xb))
> -#define CONDGU (COND(0xc))
> -#define CONDL (COND(0x3))
> -#define CONDLE (COND(0x2))
> -#define CONDLEU (COND(0x4))
> -#define CONDN (COND(0x0))
> -#define CONDNE (COND(0x9))
> -#define CONDNEG (COND(0x6))
> -#define CONDPOS (COND(0xe))
> -#define CONDVC (COND(0xf))
> -#define CONDVS (COND(0x7))
> -
> -#define CONDNZ CONDNE
> -#define CONDZ CONDE
> -#define CONDGEU CONDCC
> -#define CONDLU CONDCS
> -
> -#define FCONDA (COND(0x8))
> -#define FCONDE (COND(0x9))
> -#define FCONDG (COND(0x6))
> -#define FCONDGE (COND(0xb))
> -#define FCONDL (COND(0x4))
> -#define FCONDLE (COND(0xd))
> -#define FCONDLG (COND(0x2))
> -#define FCONDN (COND(0x0))
> -#define FCONDNE (COND(0x1))
> -#define FCONDO (COND(0xf))
> -#define FCONDU (COND(0x7))
> -#define FCONDUE (COND(0xa))
> -#define FCONDUG (COND(0x5))
> -#define FCONDUGE (COND(0xc))
> -#define FCONDUL (COND(0x3))
> -#define FCONDULE (COND(0xe))
> -
> -#define FCONDNZ FCONDNE
> -#define FCONDZ FCONDE
> -
> -#define ICC (0) /* v9 */
> -#define XCC (1<<12) /* v9 */
> -#define FCC(x) (((x)&0x3)<<11) /* v9 */
> -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
> -
> -/* The order of the opcodes in the table is significant:
> -
> - * The assembler requires that all instances of the same mnemonic must
> - be consecutive. If they aren't, the assembler will bomb at runtime.
> -
> - * The disassembler should not care about the order of the opcodes.
> -
> -*/
> -
> -/* Entries for commutative arithmetic operations. */
> -/* ??? More entries can make use of this. */
> -#define commuteop(opcode, op3, arch_mask) \
> -{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0,
> arch_mask }, \
> -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0,
> arch_mask }, \
> -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0,
> arch_mask }
> -
> -struct sparc_opcode sparc_opcodes[] = {
> -
> -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0,
> v6 },
> -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6
> }, /* ld [rs1+%g0],d */
> -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0,
> v6 },
> -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0,
> v6 },
> -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* ld [rs1+0],d */
> -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0,
> v6 },
> -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6
> }, /* ld [rs1+%g0],d */
> -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0,
> v6 },
> -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0,
> v6 },
> -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6
> },
> -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6
> }, /* ld [rs1+0],d */
> -
> -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0,
> v6 },
> -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6
> }, /* ld [rs1+%g0],d */
> -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0,
> v6 },
> -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0,
> v6 },
> -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6
> },
> -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0,
> v6 }, /* ld [rs1+0],d */
> -
> -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0,
> v6notv9 }, /* ld [rs1+%g0],d */
> -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0,
> v6notv9 }, /* ld [rs1+0],d */
> -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0,
> v6notv9 }, /* ld [rs1+%g0],d */
> -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0,
> v6notv9 },
> -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0,
> v6notv9 }, /* ld [rs1+0],d */
> -
> -/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
> - 'ld' pseudo-op in v9. */
> -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d",
> F_ALIAS, v9 },
> -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d",
> F_ALIAS, v9 }, /* ld [rs1+%g0],d */
> -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d",
> F_ALIAS, v9 },
> -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d",
> F_ALIAS, v9 },
> -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d",
> F_ALIAS, v9 },
> -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d",
> F_ALIAS, v9 }, /* ld [rs1+0],d */
> -
> -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0,
> v6 },
> -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6
> }, /* ldd [rs1+%g0],d */
> -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0,
> v6 },
> -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0,
> v6 },
> -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* ldd [rs1+0],d */
> -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0,
> v6 },
> -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6
> }, /* ldd [rs1+%g0],d */
> -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0,
> v6 },
> -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0,
> v6 },
> -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6
> },
> -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6
> }, /* ldd [rs1+0],d */
> -
> -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0,
> v6notv9 },
> -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0,
> v6notv9 }, /* ldd [rs1+%g0],d */
> -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0,
> v6notv9 },
> -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0,
> v6notv9 },
> -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0,
> v6notv9 },
> -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0,
> v6notv9 }, /* ldd [rs1+0],d */
> -
> -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0,
> v9 },
> -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9
> }, /* ldd [rs1+%g0],d */
> -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0,
> v9 },
> -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0,
> v9 },
> -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9
> },
> -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9
> }, /* ldd [rs1+0],d */
> -
> -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0,
> v6 },
> -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6
> }, /* ldsb [rs1+%g0],d */
> -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0,
> v6 },
> -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0,
> v6 },
> -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* ldsb [rs1+0],d */
> -
> -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6
> }, /* ldsh [rs1+%g0],d */
> -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0,
> v6 },
> -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0,
> v6 },
> -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0,
> v6 },
> -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* ldsh [rs1+0],d */
> -
> -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0,
> v6 },
> -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6
> }, /* ldstub [rs1+%g0],d */
> -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0,
> v6 },
> -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0,
> v6 },
> -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* ldstub [rs1+0],d */
> -
> -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0,
> v9 },
> -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9
> }, /* ldsw [rs1+%g0],d */
> -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0,
> v9 },
> -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0,
> v9 },
> -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9
> },
> -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9
> }, /* ldsw [rs1+0],d */
> -
> -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0,
> v6 },
> -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6
> }, /* ldub [rs1+%g0],d */
> -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0,
> v6 },
> -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0,
> v6 },
> -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* ldub [rs1+0],d */
> -
> -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0,
> v6 },
> -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6
> }, /* lduh [rs1+%g0],d */
> -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0,
> v6 },
> -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0,
> v6 },
> -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6
> },
> -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6
> }, /* lduh [rs1+0],d */
> -
> -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0,
> v9 },
> -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9
> }, /* ldx [rs1+%g0],d */
> -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0,
> v9 },
> -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0,
> v9 },
> -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9
> },
> -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9
> }, /* ldx [rs1+0],d */
> -
> -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0,
> v9 },
> -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),
> "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
> -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0,
> v9 },
> -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0,
> v9 },
> -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),
> "[i],F", 0, v9 },
> -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21,
> ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
> -
> -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* lda [rs1+%g0],d */
> -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0,
> v9 },
> -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9
> }, /* lda [rs1+%g0],d */
> -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0,
> v9 },
> -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0,
> v9 },
> -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9
> },
> -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* ldda [rs1+%g0],d */
> -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0,
> v9 },
> -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9
> }, /* ldda [rs1+%g0],d */
> -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0,
> v9 },
> -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0,
> v9 },
> -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9
> },
> -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0,
> v9 },
> -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9
> }, /* ldd [rs1+%g0],d */
> -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0,
> v9 },
> -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0,
> v9 },
> -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9
> },
> -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9
> }, /* ldd [rs1+0],d */
> -
> -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* ldsba [rs1+%g0],d */
> -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* ldsha [rs1+%g0],d */
> -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* ldstuba [rs1+%g0],d */
> -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0,
> v9 },
> -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9
> }, /* lda [rs1+%g0],d */
> -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* lduba [rs1+%g0],d */
> -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0,
> v6 },
> -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6
> }, /* lduha [rs1+%g0],d */
> -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d",
> F_ALIAS, v9 }, /* lduwa === lda */
> -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d",
> F_ALIAS, v9 }, /* lda [rs1+%g0],d */
> -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d",
> F_ALIAS, v9 },
> -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d",
> F_ALIAS, v9 },
> -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d",
> F_ALIAS, v9 },
> -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d",
> F_ALIAS, v9 }, /* ld [rs1+0],d */
> -
> -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0,
> v9 }, /* lduwa === lda */
> -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9
> }, /* lda [rs1+%g0],d */
> -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* ld [rs1+0],d */
> -
> -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),
> "d,[1+2]", 0, v6 },
> -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),
> "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
> -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),
> "d,[1+i]", 0, v6 },
> -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),
> "d,[i+1]", 0, v6 },
> -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,
> "d,[i]", 0, v6 },
> -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),
> "d,[1]", 0, v6 }, /* st d,[rs1+0] */
> -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),
> "g,[1+2]", 0, v6 },
> -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),
> "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
> -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),
> "g,[1+i]", 0, v6 },
> -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),
> "g,[i+1]", 0, v6 },
> -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,
> "g,[i]", 0, v6 },
> -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),
> "g,[1]", 0, v6 }, /* st d,[rs1+0] */
> -
> -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),
> "D,[1+2]", 0, v6notv9 },
> -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),
> "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
> -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),
> "D,[1+i]", 0, v6notv9 },
> -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),
> "D,[i+1]", 0, v6notv9 },
> -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,
> "D,[i]", 0, v6notv9 },
> -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),
> "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
> -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),
> "C,[1+2]", 0, v6notv9 },
> -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),
> "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
> -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),
> "C,[1+i]", 0, v6notv9 },
> -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),
> "C,[i+1]", 0, v6notv9 },
> -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,
> "C,[i]", 0, v6notv9 },
> -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),
> "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
> -
> -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),
> "F,[1+2]", 0, v6 },
> -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),
> "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
> -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,
> "F,[1+i]", 0, v6 },
> -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,
> "F,[i+1]", 0, v6 },
> -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,
> "F,[i]", 0, v6 },
> -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),
> "F,[1]", 0, v6 }, /* st d,[rs1+0] */
> -
> -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]",
> F_ALIAS, v9 },
> -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]",
> F_ALIAS, v9 }, /* st d,[rs1+%g0] */
> -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]",
> F_ALIAS, v9 },
> -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]",
> F_ALIAS, v9 },
> -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]",
> F_ALIAS, v9 },
> -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]",
> F_ALIAS, v9 }, /* st d,[rs1+0] */
> -
> -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0,
> v6 },
> -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6
> }, /* sta d,[rs1+%g0] */
> -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0,
> v9 },
> -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0,
> v9 },
> -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9
> },
> -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9
> }, /* st d,[rs1+0] */
> -
> -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0,
> v9 },
> -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9
> }, /* sta d,[rs1+%g0] */
> -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0,
> v9 },
> -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0,
> v9 },
> -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9
> },
> -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9
> }, /* st d,[rs1+0] */
> -
> -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A",
> F_ALIAS, v9 },
> -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A",
> F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
> -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o",
> F_ALIAS, v9 },
> -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o",
> F_ALIAS, v9 },
> -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o",
> F_ALIAS, v9 },
> -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o",
> F_ALIAS, v9 }, /* st d,[rs1+0] */
> -
> -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0,
> v6 },
> -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
> }, /* stb d,[rs1+%g0] */
> -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0,
> v6 },
> -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0,
> v6 },
> -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6
> },
> -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6
> }, /* stb d,[rs1+0] */
> -
> -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0,
> v6 },
> -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6
> }, /* stba d,[rs1+%g0] */
> -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0,
> v9 },
> -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0,
> v9 },
> -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9
> },
> -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9
> }, /* stb d,[rs1+0] */
> -
> -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0,
> v6 },
> -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
> }, /* std d,[rs1+%g0] */
> -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0,
> v6 },
> -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0,
> v6 },
> -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6
> },
> -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6
> }, /* std d,[rs1+0] */
> -
> -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0,
> v6notv9 }, /* std d,[rs1+%g0] */
> -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0,
> v6notv9 }, /* std d,[rs1+0] */
> -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0,
> v6 },
> -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6
> }, /* std d,[rs1+%g0] */
> -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0,
> v6 },
> -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0,
> v6 },
> -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6
> },
> -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6
> }, /* std d,[rs1+0] */
> -
> -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0,
> v6notv9 }, /* std d,[rs1+%g0] */
> -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0,
> v6notv9 }, /* std d,[rs1+0] */
> -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0,
> v6notv9 }, /* std d,[rs1+%g0] */
> -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0,
> v6notv9 },
> -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0,
> v6notv9 }, /* std d,[rs1+0] */
> -
> -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0,
> v6 },
> -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6
> }, /* stda d,[rs1+%g0] */
> -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0,
> v9 },
> -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0,
> v9 },
> -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9
> },
> -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9
> }, /* std d,[rs1+0] */
> -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0,
> v9 },
> -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9
> }, /* stda d,[rs1+%g0] */
> -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0,
> v9 },
> -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0,
> v9 },
> -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9
> },
> -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9
> }, /* std d,[rs1+0] */
> -
> -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0,
> v6 },
> -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6
> }, /* sth d,[rs1+%g0] */
> -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0,
> v6 },
> -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0,
> v6 },
> -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6
> },
> -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6
> }, /* sth d,[rs1+0] */
> -
> -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0,
> v6 },
> -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6
> }, /* stha ,[rs1+%g0] */
> -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0,
> v9 },
> -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0,
> v9 },
> -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9
> },
> -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9
> }, /* sth d,[rs1+0] */
> -
> -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0,
> v9 },
> -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9
> }, /* stx d,[rs1+%g0] */
> -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0,
> v9 },
> -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0,
> v9 },
> -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9
> },
> -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9
> }, /* stx d,[rs1+0] */
> -
> -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1),
> "F,[1+2]", 0, v9 },
> -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25,
> ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
> -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),
> "F,[1+i]", 0, v9 },
> -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),
> "F,[i+1]", 0, v9 },
> -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),
> "F,[i]", 0, v9 },
> -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25,
> ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
> -
> -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0,
> v9 },
> -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9
> }, /* stxa d,[rs1+%g0] */
> -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0,
> v9 },
> -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0,
> v9 },
> -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9
> },
> -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9
> }, /* stx d,[rs1+0] */
> -
> -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0,
> v9 },
> -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9
> }, /* stq [rs1+%g0] */
> -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0,
> v9 },
> -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0,
> v9 },
> -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9
> },
> -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9
> }, /* stq [rs1+0] */
> -
> -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0,
> v9 },
> -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9
> }, /* stqa [rs1+%g0] */
> -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0,
> v9 },
> -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0,
> v9 },
> -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9
> },
> -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9
> }, /* stqa [rs1+0] */
> -
> -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0,
> v7 },
> -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7
> }, /* swap [rs1+%g0],d */
> -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0,
> v7 },
> -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0,
> v7 },
> -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7
> },
> -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7
> }, /* swap [rs1+0],d */
> -
> -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0,
> v7 },
> -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7
> }, /* swapa [rs1+%g0],d */
> -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0,
> v9 },
> -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0,
> v9 },
> -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9
> },
> -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9
> }, /* swap [rs1+0],d */
> -
> -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),
> "1,2,d", 0, v6 },
> -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),
> "", 0, v6 }, /* restore %g0,%g0,%g0 */
> -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),
> "1,i,d", 0, v6 },
> -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),
> "", 0, v6 }, /* restore %g0,0,%g0 */
> -
> -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2",
> F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
> -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1",
> F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */
> -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i",
> F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
> -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1",
> F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
> -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i",
> F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
> -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i",
> F_UNBR|F_DELAYED, v6 }, /* rett X */
> -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1",
> F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */
> -
> -{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6
> },
> -{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6
> },
> -
> -{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),
> "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
> -{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38,
> ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
> -
> -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d",
> F_JSR|F_DELAYED, v6 },
> -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d",
> F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
> -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d",
> F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
> -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d",
> F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
> -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d",
> F_JSR|F_DELAYED, v6 },
> -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d",
> F_JSR|F_DELAYED, v6 },
> -
> -{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e,
> ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
> -{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e,
> ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
> -{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31,
> ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
> -{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31,
> ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
> -{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,
> "i", 0, v9 },
> -
> -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
> -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 },
> /* flush rs1+%g0 */
> -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 },
> /* flush rs1+0 */
> -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 },
> /* flush %g0+i */
> -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 },
> -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 },
> -
> -/* IFLUSH was renamed to FLUSH in v8. */
> -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS,
> v6 },
> -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS,
> v6 }, /* flush rs1+%g0 */
> -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS,
> v6 }, /* flush rs1+0 */
> -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS,
> v6 },
> -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS,
> v6 },
> -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS,
> v6 },
> -
> -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
> -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 },
> /* return rs1+%g0 */
> -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 },
> /* return rs1+0 */
> -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 },
> /* return %g0+i */
> -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 },
> -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 },
> -
> -{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),
> "", 0, v9 },
> -
> -{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28,
> ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
> -{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28,
> ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
> -
> -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),
> "[1+2],*", 0, v9 },
> -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0,
> "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
> -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),
> "[1+i],*", 0, v9 },
> -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),
> "[i+1],*", 0, v9 },
> -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,
> "[i],*", 0, v9 },
> -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),
> "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
> -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),
> "[1+2]A,*", 0, v9 },
> -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0,
> "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
> -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),
> "[1+i]o,*", 0, v9 },
> -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),
> "[i+1]o,*", 0, v9 },
> -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,
> "[i]o,*", 0, v9 },
> -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),
> "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
> -
> - /* The 1<<12 is a long story. It is necessary. For more info, please
> contact address@hidden */
> - /* FIXME: 'i' is wrong, need new letter for 5 bit unsigned constants. */
> -{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|ASI(~0),
> "1,2,d", 0, v6 },
> -{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12),
> "1,i,d", 0, v6 },
> -{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0),
> "1,2,d", 0, v6 },
> -{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12),
> "1,i,d", 0, v6 },
> -{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0),
> "1,2,d", 0, v6 },
> -{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12),
> "1,i,d", 0, v6 },
> -
> - /* FIXME: 'j' is wrong, need new letter for 6 bit unsigned constants. */
> -{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(ASI(~0)^(1<<12)),
> "1,2,d", 0, v9 },
> -{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),
> "1,j,d", 0, v9 },
> -{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(ASI(~0)^(1<<12)),
> "1,2,d", 0, v9 },
> -{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),
> "1,j,d", 0, v9 },
> -{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(ASI(~0)^(1<<12)),
> "1,2,d", 0, v9 },
> -{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),
> "1,j,d", 0, v9 },
> -
> -{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6
> },
> -
> -{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0,
> sparclite },
> -{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0,
> sparclite },
> -
> -{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0,
> sparclet|sparclite },
> -{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0,
> sparclet|sparclite },
> -
> -{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS2_G0|ASI(~0),"2,d", 0, v9 },
> -{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS2_G0, "i,d", 0, v9 },
> -
> -{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),
> "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
> -{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),
> "d", F_ALIAS, v6 }, /* or %g0,0,d */
> -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),
> "[1+2]", F_ALIAS, v6 },
> -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),
> "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
> -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,
> "[1+i]", F_ALIAS, v6 },
> -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,
> "[i+1]", F_ALIAS, v6 },
> -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,
> "[i]", F_ALIAS, v6 },
> -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),
> "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
> -
> -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),
> "[1+2]", F_ALIAS, v6 },
> -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]",
> F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
> -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,
> "[1+i]", F_ALIAS, v6 },
> -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,
> "[i+1]", F_ALIAS, v6 },
> -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]",
> F_ALIAS, v6 },
> -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]",
> F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
> -
> -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),
> "[1+2]", F_ALIAS, v6 },
> -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]",
> F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
> -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,
> "[1+i]", F_ALIAS, v6 },
> -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,
> "[i+1]", F_ALIAS, v6 },
> -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]",
> F_ALIAS, v6 },
> -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]",
> F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
> -
> -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),
> "[1+2]", F_ALIAS, v9 },
> -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]",
> F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
> -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,
> "[1+i]", F_ALIAS, v9 },
> -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,
> "[i+1]", F_ALIAS, v9 },
> -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]",
> F_ALIAS, v9 },
> -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]",
> F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
> -
> -{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6
> },
> -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6
> },
> -
> -/* This is not a commutative instruction. */
> -{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6
> },
> -
> -/* This is not a commutative instruction. */
> -{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6
> },
> -
> -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0,
> v6 }, /* orcc rs1, %g0, %g0 */
> -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0,
> v6 }, /* orcc %g0, rs2, %g0 */
> -{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0,
> v6 }, /* orcc rs1, 0, %g0 */
> -
> -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),
> "1,2,m", 0, v8 }, /* wr r,r,%asrX */
> -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),
> "1,2,y", 0, v6 }, /* wr r,r,%y */
> -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1),
> "1,i,m", 0, v8 }, /* wr r,i,%asrX */
> -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,
> "1,i,y", 0, v6 }, /* wr r,i,%y */
> -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),
> "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
> -{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,
> "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
> -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),
> "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
> -{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,
> "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
> -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),
> "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
> -{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,
> "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
> -
> -{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),
> "1,2,E", 0, v9 }, /* wr r,r,%ccr */
> -{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2),
> "1,i,E", 0, v9 }, /* wr r,i,%ccr */
> -{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),
> "1,2,o", 0, v9 }, /* wr r,r,%asi */
> -{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3),
> "1,i,o", 0, v9 }, /* wr r,i,%asi */
> -{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),
> "1,2,s", 0, v9 }, /* wr r,i,%fprs */
> -{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6),
> "1,i,s", 0, v9 }, /* wr r,i,%fprs */
> -
> -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),
> "M,d", 0, v8 }, /* rd %asrX,r */
> -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28,
> ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
> -{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29,
> ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
> -{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a,
> ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
> -{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b,
> ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
> -
> -{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28,
> ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
> -{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28,
> ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
> -{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28,
> ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
> -{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28,
> ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
> -{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28,
> ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
> -
> -{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d",
> 0, v9 }, /* rdpr %priv,r */
> -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0),
> "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
> -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!",
> 0, v9 }, /* wrpr r1,%priv */
> -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1),
> "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
> -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1),
> "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
> -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!",
> 0, v9 }, /* wrpr i,%priv */
> -
> -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),
> "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
> -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),
> "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
> -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1),
> "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
> -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,
> "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
> -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),
> "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
> -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,
> "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
> -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),
> "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
> -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,
> "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
> -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),
> "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
> -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,
> "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
> -
> -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),
> "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
> -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),
> "y,d", F_ALIAS, v6 }, /* rd %y,r */
> -{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),
> "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
> -{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),
> "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
> -{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),
> "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
> -
> -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,y", F_ALIAS,
> v6 }, /* wr rs1,%g0,%y */
> -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,y", F_ALIAS,
> v6 }, /* wr %g0,i,%y */
> -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,y", F_ALIAS,
> v6 }, /* wr rs1,0,%y */
> -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|ASI_RS2(~0), "1,p", F_ALIAS,
> v6notv9 }, /* wr rs1,%g0,%psr */
> -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1), "i,p", F_ALIAS,
> v6notv9 }, /* wr %g0,i,%psr */
> -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|SIMM13(~0), "1,p", F_ALIAS,
> v6notv9 }, /* wr rs1,0,%psr */
> -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|ASI_RS2(~0), "1,w", F_ALIAS,
> v6notv9 }, /* wr rs1,%g0,%wim */
> -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,w", F_ALIAS,
> v6notv9 }, /* wr %g0,i,%wim */
> -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|SIMM13(~0), "1,w", F_ALIAS,
> v6notv9 }, /* wr rs1,0,%wim */
> -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|ASI_RS2(~0), "1,t", F_ALIAS,
> v6notv9 }, /* wr rs1,%g0,%tbr */
> -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,t", F_ALIAS,
> v6notv9 }, /* wr %g0,i,%tbr */
> -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|SIMM13(~0), "1,t", F_ALIAS,
> v6notv9 }, /* wr rs1,0,%tbr */
> -
> -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d",
> 0, v6 }, /* or %g0,rs2,d */
> -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d",
> 0, v6 }, /* or %g0,i,d */
> -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),
> "1,d", 0, v6 }, /* or rs1,%g0,d */
> -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),
> "1,d", 0, v6 }, /* or rs1,0,d */
> -
> -{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6
> },
> -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6
> },
> -
> -{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS,
> v6 }, /* or rd,rs2,rd */
> -{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS,
> v6 }, /* or rd,i,rd */
> -
> -/* This is not a commutative instruction. */
> -{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6
> },
> -
> -/* This is not a commutative instruction. */
> -{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6
> },
> -
> -{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS,
> v6 }, /* andn rd,rs2,rd */
> -{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS,
> v6 }, /* andn rd,i,rd */
> -
> -{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2",
> 0, v6 }, /* subcc rs1,rs2,%g0 */
> -{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i",
> 0, v6 }, /* subcc rs1,i,%g0 */
> -
> -{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6
> },
> -
> -{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6
> },
> -
> -{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0,
> v6notv9 },
> -{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0,
> v6notv9 },
> -{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9
> },
> -
> -{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0,
> v6notv9 },
> -{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0,
> v6notv9 },
> -{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9
> },
> -
> -{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6
> },
> -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6
> },
> -
> -{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6
> },
> -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6
> },
> -
> -{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001),
> "r", F_ALIAS, v6 }, /* sub rd,1,rd */
> -{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1),
> "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */
> -{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001),
> "r", F_ALIAS, v6 }, /* subcc rd,1,rd */
> -{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1),
> "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */
> -{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001),
> "r", F_ALIAS, v6 }, /* add rd,1,rd */
> -{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1),
> "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */
> -{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001),
> "r", F_ALIAS, v6 }, /* addcc rd,1,rd */
> -{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1),
> "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */
> -
> -{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2",
> F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */
> -{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 },
> /* andcc rs1,i,%g0 */
> -
> -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d",
> F_ALIAS, v6 }, /* sub %g0,rs2,rd */
> -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS,
> v6 }, /* sub %g0,rd,rd */
> -
> -{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6
> },
> -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6
> },
> -{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6
> },
> -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6
> },
> -
> -{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0,
> v6notv9 },
> -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0,
> v6notv9 },
> -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0,
> v6notv9 },
> -{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9
> },
> -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9
> },
> -
> -{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0,
> v6notv9 },
> -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0,
> v6notv9 },
> -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0,
> v6notv9 },
> -{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9
> },
> -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9
> },
> -
> -{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8
> },
> -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8
> },
> -{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8
> },
> -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8
> },
> -{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8
> },
> -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8
> },
> -{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8
> },
> -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8
> },
> -{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8
> },
> -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8
> },
> -{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8
> },
> -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8
> },
> -{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8
> },
> -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8
> },
> -{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8
> },
> -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8
> },
> -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8
> },
> -
> -{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9
> },
> -{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9
> },
> -{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9
> },
> -{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9
> },
> -
> -{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
> -{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
> -
> -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),
> "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
> -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),
> "1+2,#", F_JSR|F_DELAYED, v6 },
> -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),
> "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
> -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),
> "1,#", F_JSR|F_DELAYED, v6 },
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
> "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
> "1+i,#", F_JSR|F_DELAYED, v6 },
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
> "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),
> "i+1,#", F_JSR|F_DELAYED, v6 },
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,
> "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,
> "i,#", F_JSR|F_DELAYED, v6 },
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),
> "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
> -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),
> "1,#", F_JSR|F_DELAYED, v6 },
> -
> -
> -/* Conditional instructions.
> -
> - Because this part of the table was such a mess earlier, I have
> - macrofied it so that all the branches and traps are generated from
> - a single-line description of each condition value. John Gilmore. */
> -
> -/* Define branches -- one annulled, one without, etc. */
> -#define br(opcode, mask, lose, flags) \
> - { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
> - { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
> -
> -#define brx(opcode, mask, lose, flags) /* v9 */ \
> - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
> - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
> - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
> - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
> - { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
> - { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
> - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
> - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
> - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
> - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
> - { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
> - { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
> -
> -/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone.
> */
> -#define tr(opcode, mask, lose, flags) \
> - { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 },
> /* %g0 + imm */ \
> - { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1
> + imm */ \
> - { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1
> + rs2 */ \
> - { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 },
> /* rs1 + %g0 */ \
> - { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 },
> /* %g0 + imm */ \
> - { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1
> + imm */ \
> - { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1
> + rs2 */ \
> - { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 },
> /* rs1 + %g0 */ \
> - { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 },
> /* %g0 + imm */ \
> - { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1
> + imm */ \
> - { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1
> + rs2 */ \
> - { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 }
> /* rs1 + %g0 */
> -
> -/* v9: We must put `brx' before `br', to ensure that we never match something
> - v9: against an expression unless it is an expression. Otherwise, we end
> - v9: up with undefined symbol tables entries, because they get added, but
> - v9: are not deleted if the pattern fails to match. */
> -
> -/* Define both branches and traps based on condition mask */
> -#define cond(bop, top, mask, flags) \
> - brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)),
> F_DELAYED|(flags)), /* v9 */ \
> - br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)),
> F_DELAYED|(flags)), \
> - tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)),
> ((flags) & ~(F_UNBR|F_CONDBR)))
> -
> -/* Define all the conditions, all the branches, all the traps. */
> -
> -/* Standard branch, trap mnemonics */
> -cond ("b", "ta", CONDA, F_UNBR),
> -/* Alternative form (just for assembly, not for disassembly) */
> -cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
> -
> -cond ("bcc", "tcc", CONDCC, F_CONDBR),
> -cond ("bcs", "tcs", CONDCS, F_CONDBR),
> -cond ("be", "te", CONDE, F_CONDBR),
> -cond ("bg", "tg", CONDG, F_CONDBR),
> -cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
> -cond ("bge", "tge", CONDGE, F_CONDBR),
> -cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
> -cond ("bgu", "tgu", CONDGU, F_CONDBR),
> -cond ("bl", "tl", CONDL, F_CONDBR),
> -cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
> -cond ("ble", "tle", CONDLE, F_CONDBR),
> -cond ("bleu", "tleu", CONDLEU, F_CONDBR),
> -cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
> -cond ("bn", "tn", CONDN, F_CONDBR),
> -cond ("bne", "tne", CONDNE, F_CONDBR),
> -cond ("bneg", "tneg", CONDNEG, F_CONDBR),
> -cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
> -cond ("bpos", "tpos", CONDPOS, F_CONDBR),
> -cond ("bvc", "tvc", CONDVC, F_CONDBR),
> -cond ("bvs", "tvs", CONDVS, F_CONDBR),
> -cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
> -
> -#undef cond
> -#undef br
> -#undef brr /* v9 */
> -#undef tr
> -
> -#define brr(opcode, mask, lose, flags) /* v9 */ \
> - { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
> - { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
> - { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
> - { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
> - { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
> - { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
> -
> -#define condr(bop, mask, flags) /* v9 */ \
> - brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
> -
> -/* v9 */ condr("brnz", 0x5, F_CONDBR),
> -/* v9 */ condr("brz", 0x1, F_CONDBR),
> -/* v9 */ condr("brgez", 0x7, F_CONDBR),
> -/* v9 */ condr("brlz", 0x3, F_CONDBR),
> -/* v9 */ condr("brlez", 0x2, F_CONDBR),
> -/* v9 */ condr("brgz", 0x6, F_CONDBR),
> -
> -#undef condr /* v9 */
> -#undef brr /* v9 */
> -
> -#define movr(opcode, mask, flags) /* v9 */ \
> - { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)),
> "1,2,d", (flags), v9 }, \
> - { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)),
> "1,j,d", (flags), v9 }
> -
> -#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
> - { opcode, (mask), (lose), "1,f,g", (flags), v9 }
> -#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
> - { opcode, (mask), (lose), "1,B,H", (flags), v9 }
> -#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
> - { opcode, (mask), (lose), "1,R,J", (flags), v9 }
> -
> -#define fmovrs(mop, mask, flags) /* v9 */ \
> - fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35,
> 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
> -#define fmovrd(mop, mask, flags) /* v9 */ \
> - fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35,
> 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
> -#define fmovrq(mop, mask, flags) /* v9 */ \
> - fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35,
> 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
> -
> -/* v9 */ movr("movrne", 0x5, 0),
> -/* v9 */ movr("movre", 0x1, 0),
> -/* v9 */ movr("movrgez", 0x7, 0),
> -/* v9 */ movr("movrlz", 0x3, 0),
> -/* v9 */ movr("movrlez", 0x2, 0),
> -/* v9 */ movr("movrgz", 0x6, 0),
> -/* v9 */ movr("movrnz", 0x5, F_ALIAS),
> -/* v9 */ movr("movrz", 0x1, F_ALIAS),
> -
> -/* v9 */ fmovrs("fmovrsne", 0x5, 0),
> -/* v9 */ fmovrs("fmovrse", 0x1, 0),
> -/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
> -/* v9 */ fmovrs("fmovrslz", 0x3, 0),
> -/* v9 */ fmovrs("fmovrslez", 0x2, 0),
> -/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
> -/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
> -/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
> -
> -/* v9 */ fmovrd("fmovrdne", 0x5, 0),
> -/* v9 */ fmovrd("fmovrde", 0x1, 0),
> -/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
> -/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
> -/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
> -/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
> -/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
> -/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
> -
> -/* v9 */ fmovrq("fmovrqne", 0x5, 0),
> -/* v9 */ fmovrq("fmovrqe", 0x1, 0),
> -/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
> -/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
> -/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
> -/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
> -/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
> -/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
> -
> -#undef movr /* v9 */
> -#undef fmovr /* v9 */
> -#undef fmrr /* v9 */
> -
> -#define movicc(opcode, cond, flags) /* v9 */ \
> - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c,
> ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c,
> ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c,
> ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c,
> ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
> -
> -#define movfcc(opcode, fcond, flags) /* v9 */ \
> - { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
> - { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0),
> MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
> -
> -#define movcc(opcode, cond, fcond, flags) /* v9 */ \
> - movfcc (opcode, fcond, flags), /* v9 */ \
> - movicc (opcode, cond, flags) /* v9 */
> -
> -/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
> -/* v9 */ movicc ("movcc", CONDCC, 0),
> -/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
> -/* v9 */ movicc ("movcs", CONDCS, 0),
> -/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
> -/* v9 */ movcc ("move", CONDE, FCONDE, 0),
> -/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
> -/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
> -/* v9 */ movicc ("movgu", CONDGU, 0),
> -/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
> -/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
> -/* v9 */ movicc ("movleu", CONDLEU, 0),
> -/* v9 */ movfcc ("movlg", FCONDLG, 0),
> -/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
> -/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
> -/* v9 */ movicc ("movneg", CONDNEG, 0),
> -/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
> -/* v9 */ movfcc ("movo", FCONDO, 0),
> -/* v9 */ movicc ("movpos", CONDPOS, 0),
> -/* v9 */ movfcc ("movu", FCONDU, 0),
> -/* v9 */ movfcc ("movue", FCONDUE, 0),
> -/* v9 */ movfcc ("movug", FCONDUG, 0),
> -/* v9 */ movfcc ("movuge", FCONDUGE, 0),
> -/* v9 */ movfcc ("movul", FCONDUL, 0),
> -/* v9 */ movfcc ("movule", FCONDULE, 0),
> -/* v9 */ movicc ("movvc", CONDVC, 0),
> -/* v9 */ movicc ("movvs", CONDVS, 0),
> -/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
> -
> -#undef movicc /* v9 */
> -#undef movfcc /* v9 */
> -#undef movcc /* v9 */
> -
> -#define FM_SF 1 /* v9 - values for fpsize */
> -#define FM_DF 2 /* v9 */
> -#define FM_QF 3 /* v9 */
> -
> -#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \
> -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35,
> ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35,
> ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 }
> -
> -#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \
> -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
> -
> -/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
> -#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \
> -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35,
> ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35,
> ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
> -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35,
> ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
> -
> -/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0),
> -/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0),
> -/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0),
> -/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0),
> -/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0),
> -/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0),
> -/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0),
> -/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0),
> -/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0),
> -/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0),
> -/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0),
> -/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0),
> -/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0),
> -/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0),
> -/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0),
> -/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0),
> -/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0),
> -/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0),
> -/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS),
> -/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS),
> -/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS),
> -/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0),
> -/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0),
> -/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0),
> -/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0),
> -/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0),
> -/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0),
> -/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0),
> -/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0),
> -/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0),
> -/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0),
> -/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0),
> -/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0),
> -/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0),
> -/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0),
> -/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0),
> -/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS),
> -/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS),
> -/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS),
> -/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0),
> -/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0),
> -/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0),
> -/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0),
> -/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0),
> -/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0),
> -/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0),
> -/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0),
> -/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0),
> -/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS),
> -/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS),
> -/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS),
> -/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0),
> -/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0),
> -/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0),
> -/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0),
> -/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0),
> -/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0),
> -/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0),
> -/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0),
> -/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0),
> -/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0),
> -/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0),
> -/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0),
> -/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0),
> -/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0),
> -/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0),
> -/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0),
> -/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0),
> -/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0),
> -/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0),
> -/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0),
> -/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0),
> -/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0),
> -/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0),
> -/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0),
> -/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0),
> -/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0),
> -/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0),
> -/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0),
> -/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0),
> -/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0),
> -/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS),
> -/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS),
> -/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS),
> -
> -#undef fmovicc /* v9 */
> -#undef fmovfcc /* v9 */
> -#undef fmovcc /* v9 */
> -#undef FM_DF /* v9 */
> -#undef FM_QF /* v9 */
> -#undef FM_SF /* v9 */
> -
> -#define brfc(opcode, mask, lose, flags) \
> - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, v6 }, \
> - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, v6 }
> -
> -#define brfcx(opcode, mask, lose, flags) /* v9 */ \
> - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",
> flags|F_DELAYED, v9 }, \
> - { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G",
> flags|F_DELAYED, v9 }
> -
> -/* v9: We must put `brfcx' before `brfc', to ensure that we never match
> - v9: something against an expression unless it is an expression.
> Otherwise,
> - v9: we end up with undefined symbol tables entries, because they get
> added,
> - v9: but are not deleted if the pattern fails to match. */
> -
> -#define condfc(fop, cop, mask, flags) \
> - brfcx(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */
> \
> - brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
> - brfc(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags)
> -
> -#define condf(fop, mask, flags) \
> - brfcx(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */
> \
> - brfc(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
> -
> -condfc("fb", "cb", 0x8, 0),
> -condfc("fba", "cba", 0x8, F_ALIAS),
> -condfc("fbe", "cb0", 0x9, 0),
> -condf("fbz", 0x9, F_ALIAS),
> -condfc("fbg", "cb2", 0x6, 0),
> -condfc("fbge", "cb02", 0xb, 0),
> -condfc("fbl", "cb1", 0x4, 0),
> -condfc("fble", "cb01", 0xd, 0),
> -condfc("fblg", "cb12", 0x2, 0),
> -condfc("fbn", "cbn", 0x0, 0),
> -condfc("fbne", "cb123", 0x1, 0),
> -condf("fbnz", 0x1, F_ALIAS),
> -condfc("fbo", "cb012", 0xf, 0),
> -condfc("fbu", "cb3", 0x7, 0),
> -condfc("fbue", "cb03", 0xa, 0),
> -condfc("fbug", "cb23", 0x5, 0),
> -condfc("fbuge", "cb023", 0xc, 0),
> -condfc("fbul", "cb13", 0x3, 0),
> -condfc("fbule", "cb013", 0xe, 0),
> -
> -#undef condfc
> -#undef brfc
> -#undef brfcx /* v9 */
> -
> -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2",
> F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
> -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1",
> F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
> -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i",
> F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
> -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1",
> F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
> -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i",
> F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
> -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1",
> F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
> -
> -{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
> -
> -{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 },
> -
> -{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
> -
> -{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6
> },
> -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6
> },
> -{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),
> "1,2,d", 0, v6 },
> -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1),
> "1,i,d", 0, v6 },
> -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1),
> "i,1,d", 0, v6 },
> -
> -{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6
> },
> -{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),
> "1,2,d", 0, v6 },
> -{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1),
> "1,i,d", 0, v6 },
> -
> -{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
> -{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
> -
> -/* This *is* a commutative instruction. */
> -{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6
> },
> -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6
> },
> -/* This *is* a commutative instruction. */
> -{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6
> },
> -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6
> },
> -{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6
> },
> -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6
> },
> -{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6
> },
> -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6
> },
> -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6
> },
> -
> -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6
> }, /* xnor rs1,%0,rd */
> -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 },
> /* xnor rd,%0,rd */
> -
> -{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS,
> v6 }, /* xor rd,rs2,rd */
> -{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS,
> v6 }, /* xor rd,i,rd */
> -
> -/* FPop1 and FPop2 are not instructions. Don't accept them. */
> -
> -{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", 0,
> v6 },
> -{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", 0,
> v6 },
> -{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", 0,
> v8 },
> -
> -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", 0,
> v9 },
> -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", 0,
> v9 },
> -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", 0,
> v9 },
> -
> -{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", 0,
> v6 },
> -{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", 0,
> v6 },
> -{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", 0,
> v8 },
> -
> -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", 0,
> v9 },
> -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", 0,
> v9 },
> -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", 0,
> v9 },
> -
> -{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", 0,
> v8 },
> -{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", 0,
> v6 },
> -{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", 0,
> v8 },
> -{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", 0,
> v8 },
> -{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", 0,
> v6 },
> -{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", 0,
> v8 },
> -
> -{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", 0, v6 },
> -{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", 0, v8 },
> -{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", 0, v6 },
> -{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", 0, v6 },
> -{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", 0, v8 },
> -{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", 0, v6 },
> -
> -{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", 0, v8 },
> -{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", 0, v8 },
> -
> -{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", 0,
> v7 },
> -{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", 0,
> v8 },
> -{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", 0,
> v7 },
> -
> -{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", 0,
> v9 },
> -{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", 0,
> v9 },
> -{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", 0,
> v6 },
> -{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", 0,
> v9 },
> -{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", 0,
> v9 },
> -{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", 0,
> v6 },
> -{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", 0,
> v9 },
> -{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", 0,
> v9 },
> -{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", 0,
> v6 },
> -
> -{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", 0, v6 },
> -{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", 0, v8 },
> -{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", 0, v6 },
> -{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", 0, v6 },
> -{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", 0, v8 },
> -{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", 0, v6 },
> -
> -#define CMPFCC(x) (((x)&0x3)<<25)
> -
> -{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35,
> ~0x052)|RD_G0, "v,B", 0, v6 },
> -{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35,
> ~0x052), "6,v,B", 0, v9 },
> -{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35,
> ~0x052), "7,v,B", 0, v9 },
> -{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35,
> ~0x052), "8,v,B", 0, v9 },
> -{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35,
> ~0x052), "9,v,B", 0, v9 },
> -{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35,
> ~0x056)|RD_G0, "v,B", 0, v6 },
> -{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35,
> ~0x056), "6,v,B", 0, v9 },
> -{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35,
> ~0x056), "7,v,B", 0, v9 },
> -{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35,
> ~0x056), "8,v,B", 0, v9 },
> -{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35,
> ~0x056), "9,v,B", 0, v9 },
> -{ "fcmpq", F3F(2, 0x34, 0x053), F3F(~2, ~0x34,
> ~0x053)|RD_G0, "V,R", 0, v8 },
> -{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35,
> ~0x053), "6,V,R", 0, v9 },
> -{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35,
> ~0x053), "7,V,R", 0, v9 },
> -{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35,
> ~0x053), "8,V,R", 0, v9 },
> -{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35,
> ~0x053), "9,V,R", 0, v9 },
> -{ "fcmpeq", F3F(2, 0x34, 0x057), F3F(~2, ~0x34,
> ~0x057)|RD_G0, "V,R", 0, v8 },
> -{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35,
> ~0x057), "6,V,R", 0, v9 },
> -{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35,
> ~0x057), "7,V,R", 0, v9 },
> -{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35,
> ~0x057), "8,V,R", 0, v9 },
> -{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35,
> ~0x057), "9,V,R", 0, v9 },
> -{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35,
> ~0x051)|RD_G0, "e,f", 0, v6 },
> -{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35,
> ~0x051), "6,e,f", 0, v9 },
> -{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35,
> ~0x051), "7,e,f", 0, v9 },
> -{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35,
> ~0x051), "8,e,f", 0, v9 },
> -{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35,
> ~0x051), "9,e,f", 0, v9 },
> -{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35,
> ~0x055)|RD_G0, "e,f", 0, v6 },
> -{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35,
> ~0x055), "6,e,f", 0, v9 },
> -{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35,
> ~0x055), "7,e,f", 0, v9 },
> -{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35,
> ~0x055), "8,e,f", 0, v9 },
> -{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35,
> ~0x055), "9,e,f", 0, v9 },
> -
> -/* These Extended FPop (FIFO) instructions are new in the Fujitsu
> - MB86934, replacing the CPop instructions from v6 and later
> - processors. */
> -
> -#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36,
> ~op)|RS1_G0, args, 0, sparclite }
> -#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36,
> ~op), args, 0, sparclite }
> -#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37,
> ~op)|RD_G0, args, 0, sparclite }
> -
> -EFPOP1_2 ("efitod", 0x0c8, "f,H"),
> -EFPOP1_2 ("efitos", 0x0c4, "f,g"),
> -EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
> -EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
> -EFPOP1_2 ("efstod", 0x0c9, "f,H"),
> -EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
> -EFPOP1_2 ("efmovs", 0x001, "f,g"),
> -EFPOP1_2 ("efnegs", 0x005, "f,g"),
> -EFPOP1_2 ("efabss", 0x009, "f,g"),
> -EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
> -EFPOP1_2 ("efsqrts", 0x029, "f,g"),
> -EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
> -EFPOP1_3 ("efadds", 0x041, "e,f,g"),
> -EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
> -EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
> -EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
> -EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
> -EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
> -EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
> -EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
> -EFPOP2_2 ("efcmpd", 0x052, "v,B"),
> -EFPOP2_2 ("efcmped", 0x056, "v,B"),
> -EFPOP2_2 ("efcmps", 0x051, "e,f"),
> -EFPOP2_2 ("efcmpes", 0x055, "e,f"),
> -
> -#undef EFPOP1_2
> -#undef EFPOP1_3
> -#undef EFPOP2_2
> -
> -/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
> - present. Otherwise, the F_ALIAS flag is ignored. */
> -{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9
> },
> -{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9
> },
> -
> -/* sparclet specific insns */
> -
> -commuteop ("umac", 0x3e, sparclet),
> -commuteop ("smac", 0x3f, sparclet),
> -commuteop ("umacd", 0x2e, sparclet),
> -commuteop ("smacd", 0x2f, sparclet),
> -commuteop ("umuld", 0x09, sparclet),
> -commuteop ("smuld", 0x0d, sparclet),
> -
> -{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0,
> sparclet },
> -{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0,
> sparclet },
> -
> -{ "crdcxt", F3(2, 0x36, 0)|ASI(4), F3(~2, ~0x36, ~0)|ASI(~4)|RS2(~0),
> "U,d", 0, sparclet },
> -{ "cwrcxt", F3(2, 0x36, 0)|ASI(3), F3(~2, ~0x36, ~0)|ASI(~3)|RS2(~0),
> "1,u", 0, sparclet },
> -{ "cpush", F3(2, 0x36, 0)|ASI(0), F3(~2, ~0x36, ~0)|ASI(~0)|RD(~0),
> "1,2", 0, sparclet },
> -{ "cpusha", F3(2, 0x36, 0)|ASI(1), F3(~2, ~0x36, ~0)|ASI(~1)|RD(~0),
> "1,2", 0, sparclet },
> -{ "cpull", F3(2, 0x36, 0)|ASI(2), F3(~2, ~0x36,
> ~0)|ASI(~2)|RS1(~0)|RS2(~0), "d", 0, sparclet },
> -
> -/* sparclet coprocessor branch insns */
> -/* FIXME: We have to mark these as aliases until we can sort opcodes based
> - on selected cpu. */
> -#define slcbcc2(opcode, mask, lose) \
> - { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR|F_ALIAS,
> sparclet }, \
> - { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR|F_ALIAS,
> sparclet }
> -#define slcbcc(opcode, mask) \
> - slcbcc2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
> -
> -/*slcbcc("cbn", 0), - already defined */
> -slcbcc("cbe", 1),
> -slcbcc("cbf", 2),
> -slcbcc("cbef", 3),
> -slcbcc("cbr", 4),
> -slcbcc("cber", 5),
> -slcbcc("cbfr", 6),
> -slcbcc("cbefr", 7),
> -/*slcbcc("cba", 8), - already defined */
> -slcbcc("cbne", 9),
> -slcbcc("cbnf", 10),
> -slcbcc("cbnef", 11),
> -slcbcc("cbnr", 12),
> -slcbcc("cbner", 13),
> -slcbcc("cbnfr", 14),
> -slcbcc("cbnefr", 15),
> -
> -#undef slcbcc2
> -#undef slcbcc
> -
> -/* More v9 specific insns */
> -
> -#define IMPDEP(name, code) \
> -{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9 }, \
> -{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9 }, \
> -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9 }, \
> -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9 }
> -
> -IMPDEP ("impdep1", 0x36),
> -IMPDEP ("impdep2", 0x37),
> -
> -#undef IMPDEP
> -
> -{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
> -{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
> -{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
> -{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
> -
> -/* v9 synthetic insns */
> -/* FIXME: still missing "signx d", and "clruw d". Can't be done here. */
> -{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0,
> ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
> -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0,
> "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
> -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0,
> "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
> -{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80),
> "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
> -{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88),
> "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
> -{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80),
> "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
> -{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88),
> "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
> -
> -/* Ultrasparc extensions */
> -/* FIXME: lots more to go */
> -{ "shutdown", F3F(2, 0x36, 0x80), F3(~2, ~0x36,
> ~0x80)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
> -
> -};
> -
> -const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof
> sparc_opcodes[0]));
> -
> -/* Utilities for argument parsing. */
> -
> -typedef struct
> -{
> - int value;
> - char *name;
> -} arg;
> -
> -/* Look up NAME in TABLE. */
> -
> -static int
> -lookup_name (table, name)
> - arg *table;
> - char *name;
> -{
> - arg *p;
> -
> - for (p = table; p->name; ++p)
> - if (strcmp (name, p->name) == 0)
> - return p->value;
> -
> - return -1;
> -}
> -
> -/* Look up VALUE in TABLE. */
> -
> -static char *
> -lookup_value (table, value)
> - arg *table;
> - int value;
> -{
> - arg *p;
> -
> - for (p = table; p->name; ++p)
> - if (value == p->value)
> - return p->name;
> -
> - return (char *) 0;
> -}
> -
> -/* Handle ASI's. */
> -
> -static arg asi_table[] =
> -{
> - { 0x10, "#ASI_AIUP" },
> - { 0x11, "#ASI_AIUS" },
> - { 0x18, "#ASI_AIUP_L" },
> - { 0x19, "#ASI_AIUS_L" },
> - { 0x80, "#ASI_P" },
> - { 0x81, "#ASI_S" },
> - { 0x82, "#ASI_PNF" },
> - { 0x83, "#ASI_SNF" },
> - { 0x88, "#ASI_P_L" },
> - { 0x89, "#ASI_S_L" },
> - { 0x8a, "#ASI_PNF_L" },
> - { 0x8b, "#ASI_SNF_L" },
> - { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
> - { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
> - { 0x18, "#ASI_AS_IF_USER_PRIMARY_L" },
> - { 0x19, "#ASI_AS_IF_USER_SECONDARY_L" },
> - { 0x80, "#ASI_PRIMARY" },
> - { 0x81, "#ASI_SECONDARY" },
> - { 0x82, "#ASI_PRIMARY_NOFAULT" },
> - { 0x83, "#ASI_SECONDARY_NOFAULT" },
> - { 0x88, "#ASI_PRIMARY_LITTLE" },
> - { 0x89, "#ASI_SECONDARY_LITTLE" },
> - { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
> - { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
> - { 0, 0 }
> -};
> -
> -/* Return the value for ASI NAME, or -1 if not found. */
> -
> -int
> -sparc_encode_asi (name)
> - char *name;
> -{
> - return lookup_name (asi_table, name);
> -}
> -
> -/* Return the name for ASI value VALUE or NULL if not found. */
> -
> -char *
> -sparc_decode_asi (value)
> - int value;
> -{
> - return lookup_value (asi_table, value);
> -}
> -
> -/* Handle membar masks. */
> -
> -static arg membar_table[] =
> -{
> - { 0x40, "#Sync" },
> - { 0x20, "#MemIssue" },
> - { 0x10, "#Lookaside" },
> - { 0x08, "#StoreStore" },
> - { 0x04, "#LoadStore" },
> - { 0x02, "#StoreLoad" },
> - { 0x01, "#LoadLoad" },
> - { 0, 0 }
> -};
> -
> -/* Return the value for membar arg NAME, or -1 if not found. */
> -
> -int
> -sparc_encode_membar (name)
> - char *name;
> -{
> - return lookup_name (membar_table, name);
> -}
> -
> -/* Return the name for membar value VALUE or NULL if not found. */
> -
> -char *
> -sparc_decode_membar (value)
> - int value;
> -{
> - return lookup_value (membar_table, value);
> -}
> -
> -/* Handle prefetch args. */
> -
> -static arg prefetch_table[] =
> -{
> - { 0, "#n_reads" },
> - { 1, "#one_read" },
> - { 2, "#n_writes" },
> - { 3, "#one_write" },
> - { 4, "#page" },
> - { 0, 0 }
> -};
> -
> -/* Return the value for prefetch arg NAME, or -1 if not found. */
> -
> -int
> -sparc_encode_prefetch (name)
> - char *name;
> -{
> - return lookup_name (prefetch_table, name);
> -}
> -
> -/* Return the name for prefetch value VALUE or NULL if not found. */
> -
> -char *
> -sparc_decode_prefetch (value)
> - int value;
> -{
> - return lookup_value (prefetch_table, value);
> -}
> -
> -/* Handle sparclet coprocessor registers. */
> -
> -static arg sparclet_cpreg_table[] =
> -{
> - { 0, "%ccsr" },
> - { 1, "%ccfr" },
> - { 2, "%cccrcr" },
> - { 3, "%ccpr" },
> - { 0, 0 }
> -};
> -
> -/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
> -
> -int
> -sparc_encode_sparclet_cpreg (name)
> - char *name;
> -{
> - return lookup_name (sparclet_cpreg_table, name);
> -}
> -
> -/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
> -
> -char *
> -sparc_decode_sparclet_cpreg (value)
> - int value;
> -{
> - return lookup_value (sparclet_cpreg_table, value);
> -}
> diff --git a/opcode/sparc.h b/opcode/sparc.h
> deleted file mode 100644
> index 014a534..0000000
> --- a/opcode/sparc.h
> +++ /dev/null
> @@ -1,220 +0,0 @@
> -/* Definitions for opcode table for the sparc.
> - Copyright (C) 1989, 1991, 1992, 1995, 1996 Free Software Foundation, Inc.
> -
> -This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
> -the GNU Binutils.
> -
> -GAS/GDB is free software; you can redistribute it and/or modify
> -it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 2, or (at your option)
> -any later version.
> -
> -GAS/GDB is distributed in the hope that it will be useful,
> -but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -GNU General Public License for more details.
> -
> -You should have received a copy of the GNU General Public License
> -along with GAS or GDB; see the file COPYING. If not, write to
> -the Free Software Foundation, 51 Franklin Street, Fifth Floor,
> -Boston, MA 02110-1301, USA. */
> -
> -/* The SPARC opcode table (and other related data) is defined in
> - the opcodes library in sparc-opc.c. If you change anything here, make
> - sure you fix up that file, and vice versa. */
> -
> - /* FIXME-someday: perhaps the ,a's and such should be embedded in the
> - instruction's name rather than the args. This would make gas faster,
> pinsn
> - slower, but would mess up some macros a bit. xoxorich. */
> -
> -/* List of instruction sets variations.
> - These values are such that each element is either a superset of a
> - preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
> - returns non-zero.
> - The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
> - Don't change this without updating sparc-opc.c. */
> -
> -enum sparc_opcode_arch_val {
> - SPARC_OPCODE_ARCH_V6 = 0,
> - SPARC_OPCODE_ARCH_V7,
> - SPARC_OPCODE_ARCH_V8,
> - SPARC_OPCODE_ARCH_SPARCLET,
> - SPARC_OPCODE_ARCH_SPARCLITE,
> - /* v9 variants must appear last */
> - SPARC_OPCODE_ARCH_V9,
> - SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
> - SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
> -};
> -
> -/* The highest architecture in the table. */
> -#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
> -
> -/* Table of cpu variants. */
> -
> -struct sparc_opcode_arch {
> - const char *name;
> - /* Mask of sparc_opcode_arch_val's supported.
> - EG: For v7 this would be ((1 << v6) | (1 << v7)). */
> - /* These are short's because sparc_opcode.architecture is. */
> - short supported;
> -};
> -
> -extern const struct sparc_opcode_arch sparc_opcode_archs[];
> -
> -/* Given architecture name, look up it's sparc_opcode_arch_val value. */
> -extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch ();
> -
> -/* Return the bitmask of supported architectures for ARCH. */
> -#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
> -
> -/* Non-zero if ARCH1 conflicts with ARCH2.
> - IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
> -#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
> -(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
> - != SPARC_OPCODE_SUPPORTED (ARCH1)) \
> - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
> - != SPARC_OPCODE_SUPPORTED (ARCH2)))
> -
> -/* Structure of an opcode table entry. */
> -
> -struct sparc_opcode {
> - const char *name;
> - unsigned long match; /* Bits that must be set. */
> - unsigned long lose; /* Bits that must not be set. */
> - const char *args;
> - /* This was called "delayed" in versions before the flags. */
> - char flags;
> - short architecture; /* Bitmask of sparc_opcode_arch_val's. */
> -};
> -
> -#define F_DELAYED 1 /* Delayed branch */
> -#define F_ALIAS 2 /* Alias for a "real" instruction */
> -#define F_UNBR 4 /* Unconditional branch */
> -#define F_CONDBR 8 /* Conditional branch */
> -#define F_JSR 16 /* Subroutine call */
> -/* FIXME: Add F_ANACHRONISTIC flag for v9. */
> -
> -/*
> -
> -All sparc opcodes are 32 bits, except for the `set' instruction (really a
> -macro), which is 64 bits. It is handled as a special case.
> -
> -The match component is a mask saying which bits must match a particular
> -opcode in order for an instruction to be an instance of that opcode.
> -
> -The args component is a string containing one character for each operand of
> the
> -instruction.
> -
> -Kinds of operands:
> - # Number used by optimizer. It is ignored.
> - 1 rs1 register.
> - 2 rs2 register.
> - d rd register.
> - e frs1 floating point register.
> - v frs1 floating point register (double/even).
> - V frs1 floating point register (quad/multiple of 4).
> - f frs2 floating point register.
> - B frs2 floating point register (double/even).
> - R frs2 floating point register (quad/multiple of 4).
> - g frsd floating point register.
> - H frsd floating point register (double/even).
> - J frsd floating point register (quad/multiple of 4).
> - b crs1 coprocessor register
> - c crs2 coprocessor register
> - D crsd coprocessor register
> - m alternate space register (asr) in rd
> - M alternate space register (asr) in rs1
> - h 22 high bits.
> - K MEMBAR mask (7 bits). (v9)
> - j 10 bit Immediate. (v9)
> - I 11 bit Immediate. (v9)
> - i 13 bit Immediate.
> - n 22 bit immediate.
> - k 2+14 bit PC relative immediate. (v9)
> - G 19 bit PC relative immediate. (v9)
> - l 22 bit PC relative immediate.
> - L 30 bit PC relative immediate.
> - a Annul. The annul bit is set.
> - A Alternate address space. Stored as 8 bits.
> - C Coprocessor state register.
> - F floating point state register.
> - p Processor state register.
> - N Branch predict clear ",pn" (v9)
> - T Branch predict set ",pt" (v9)
> - z %icc. (v9)
> - Z %xcc. (v9)
> - q Floating point queue.
> - r Single register that is both rs1 and rd.
> - O Single register that is both rs2 and rd.
> - Q Coprocessor queue.
> - S Special case.
> - t Trap base register.
> - w Window invalid mask register.
> - y Y register.
> - u sparclet coprocessor registers in rd position
> - U sparclet coprocessor registers in rs1 position
> - E %ccr. (v9)
> - s %fprs. (v9)
> - P %pc. (v9)
> - W %tick. (v9)
> - o %asi. (v9)
> - 6 %fcc0. (v9)
> - 7 %fcc1. (v9)
> - 8 %fcc2. (v9)
> - 9 %fcc3. (v9)
> - ! Privileged Register in rd (v9)
> - ? Privileged Register in rs1 (v9)
> - * Prefetch function constant. (v9)
> - x OPF field (v9 impdep).
> -
> -The following chars are unused: (note: ,[] are used as punctuation)
> -[XY3450]
> -
> -*/
> -
> -#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns
> */
> -#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3
> insns */
> -#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all
> insns */
> -#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns
> */
> -#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
> -#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
> -#define F3I(x) (((x)&0x1) << 13) /* immediate field of format
> 3 insns */
> -#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
> -#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
> -#define F1(x) (OP(x))
> -#define DISP30(x) ((x)&0x3fffffff)
> -#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns
> */
> -#define RS2(x) ((x)&0x1f) /* rs2 field */
> -#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
> -#define RD(x) (((x)&0x1f) << 25) /* destination register
> field */
> -#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
> -#define ASI_RS2(x) (SIMM13(x))
> -#define MEMBAR(x) ((x)&0x7f)
> -
> -#define ANNUL (1<<29)
> -#define BPRED (1<<19) /* v9 */
> -#define IMMED F3I(1)
> -#define RD_G0 RD(~0)
> -#define RS1_G0 RS1(~0)
> -#define RS2_G0 RS2(~0)
> -
> -extern struct sparc_opcode sparc_opcodes[];
> -extern const int sparc_num_opcodes;
> -
> -int sparc_encode_asi ();
> -char *sparc_decode_asi ();
> -int sparc_encode_membar ();
> -char *sparc_decode_membar ();
> -int sparc_encode_prefetch ();
> -char *sparc_decode_prefetch ();
> -int sparc_encode_sparclet_cpreg ();
> -char *sparc_decode_sparclet_cpreg ();
> -
> -/*
> - * Local Variables:
> - * fill-column: 131
> - * comment-column: 0
> - * End:
> - */
> -
> -/* end of sparc.h */
> diff --git a/opcode/sysdep.h b/opcode/sysdep.h
> deleted file mode 100644
> index b81e923..0000000
> --- a/opcode/sysdep.h
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#include <stdio.h>
> -#include <stdlib.h>
> -#include <string.h>
>
Ok.
Paolo
- Re: [Help-smalltalk] [PATCH 09/15] gtktools: Introduce a GTKTools package with helper classes, (continued)
- [Help-smalltalk] [PATCH 15/15] tooling: Introduce a helper for a Monticello export, Holger Hans Peter Freyther, 2013/04/08
- [Help-smalltalk] [PATCH 11/15] gtktools: Move the GtkSideBarWidget from VisualGST to GTKTools, Holger Hans Peter Freyther, 2013/04/08
- [Help-smalltalk] [PATCH 14/15] tooling: Introduce a new package for tooling helpers, Holger Hans Peter Freyther, 2013/04/08
- [Help-smalltalk] [PATCH 12/15] gtktools: Move model classes from VisualGST to GTKTools, Holger Hans Peter Freyther, 2013/04/08
- [Help-smalltalk] [PATCH 13/15] gtktools: Move the Clock/Tetris to the GTKTools, Holger Hans Peter Freyther, 2013/04/08
- Re: [Help-smalltalk] [PATCH 01/15] opcode: Remove the copy of the binutils code from the repository,
Paolo Bonzini <=