[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Lightning] About 32 and 64 bits registers

From: Paulo César Pereira de Andrade
Subject: Re: [Lightning] About 32 and 64 bits registers
Date: Mon, 23 Aug 2010 21:30:57 -0300
User-agent: SquirrelMail/1.4.19

Paulo César Pereira de Andrade wrote:
>   Hi,
>   How is it expected to handle proper sign/zero extension when there
> are no named 8/16/32/64 bit registers, that is, there is no JIT_R0c,
> JIT_R0s, JIT_R0i and/or JIT_R0l.
>   This has a nasty side effect that some operations must be sign/zero
> extended, for example, when loading data from a memory location. But
> then, some operations become somewhat hard to explain, for example:
>   jit_bltr_i LABEL, JIT_R0, IMMEDIATE
> this should be understood as "treated JIT_R0 value as 32 bits, but
> signed extend it, as well as immediate" ? or even better, only sign
> extend to 64 bits if there is no 32 bits equivalent operation.
> But to do an "optimized" operation, it must ensure that JIT_R0 is
> actually holding a 64 bits value.
>   Or another example:
>   jit_movi_i JIT_R0 IMMEDIATE
> this should be just an alias to jit_movi_l on 64 bits, or, better
> saying, should be more like:
>   jit_movi_i JIT_R0 (cast_to_int_32)IMMEDIATE

  I am adding what is for now an RFC about this issue, and the start
of another set of patches for x86_64. This shows one option of
creating jit_namex_{ri,r} "helper macros", that would basically
become jit_namei_* on 32 bits, and jit_namel_* on 64 bits, and
this way, ensuring the value in a register is properly sign/zero

  This is only an issue when _ASM_SAFETY is defined, and, in some
points is caused by patch6 in the "Updates for x86_64" email, but
if did not add the changes in patch6, it would not have gone this
far :-), The problem is that patch6 changes some of core-64.h to
"map" JIT_R* to 64 bit registers instead of 32 bit ones, otherwise,
it is a chicken and egg problem, where now it fails some assertions
due to using a 64 bits register on 32 bit operations, and before
it would fail due to using a 32 bits register on 64 bits operations.

  Please review/comment.


Attachment: 0007-RFC-patch-about-handling-32-and-64-bits-registers-an.patch
Description: Text Data

reply via email to

[Prev in Thread] Current Thread [Next in Thread]