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Re: [Lightning] x86_64 (System V AMD64 ABI): %r12

From: Paulo César Pereira de Andrade
Subject: Re: [Lightning] x86_64 (System V AMD64 ABI): %r12
Date: Mon, 4 Sep 2017 16:36:31 -0400

2017-09-04 16:09 GMT-04:00 Marc Nieper-Wißkirchen <address@hidden>:
> I don't understand the purpose of the hack to have 4 caller-saved registers
> and 4 callee-saved registers instead of 3 caller-saved and 5 callee-saved
> registers.
> Callee-saved registers come with a cost because they have to be saved and
> restored at function prologue and epilogue (when they are used at all). With
> the hack, lightning has to pay the cost for %r12, but the user code cannot
> exploit the benefits of callee-saved registers because user code does not
> know that %12 (or JIT_R4) is callee-saved and will have to assume that
> overwritten at each function call.
> In other words, having only 3 JIT_R? and 5 JIT_V? is in any case better than
> having 4 JIT_R? and 4 JIT_V?.

  Originally, lightning did intend to export 3 scratch registers, 3 calee save
registers and 6 float registers. This was like a random decision at the moment,
and way before other ports, like aarch64 that has up to JIT_R6 and JIT_V9.
One example where there are 3 scratch and 14 (or 17 if old abi) callee save
registers is power pc.

  The fact that jit_callee_save_p lies about JIT_R3 is a good reason to
use your suggestion. I will probably do it, and keep the suggestion at high
priority for the next lightning release.

> Marc


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