Hi,
I have never seen a 100Mbit MAC with linked DMA buffers which did not
support buffers of different sizes...
Usually you have some kind of "buffer descriptor" for each buffer, and
in that descriptor you enter the size and address of the actual buffer,
as well as a reference to the next buffer descriptor in the chain.
This usually maps very well to the linked PBUFs of lwip.
My FEC has a BUF_SIZE_REGISTER(0r something like that) which determines the maximum size of the payload buffer of the buffer descriptor unfortunately. That is at least the case with me. I wonder if Bill knows more since he has worked with PowerPC architecture with lwip before.
Regards, Ikhwan
Date: Tue, 27 May 2008 23:07:52 +0200 From: address@hidden To: address@hidden Subject: Re: [lwip-users] Misalignment problems on PowerPC (little endian mode)
I have never seen a 100Mbit MAC with linked DMA buffers which did not
support buffers of different sizes...
Usually you have some kind of "buffer descriptor" for each buffer, and
in that descriptor you enter the size and address of the actual buffer,
as well as a reference to the next buffer descriptor in the chain.
This usually maps very well to the linked PBUFs of lwip.
But I guess there could be a MAC or two out there with buffer size
limitations.
/Timmy
Muhamad Ikhwan Ismail wrote:
Hi Timmy,
It did cross my mind but unfortunately I could only set single value as
the FEC buffer size (unless I am misinformed by the user guide).
Greetings,
Ikhwan
Date: Sun, 25 May 2008 17:47:36 +0200
From: address@hidden
To: address@hidden
Subject: Re: [lwip-users] Misalignment problems on PowerPC (little
endian mode)
If your FEC does not allow storing of packets at an 2 byte offset, then
you could try setting up the FEC to store the Ethernet header in one
small PBUF, and the rest of the packet in a large 1500 byte PBUF. That
way your IP headers will be aligned.
The downside is of course that for this to work all incomming packets
regardless of size will use the full 1500 bytes.
You would need to setup every other pbuf in the FEC Rx DMA chain to 14
bytes and 1500 bytes respectively.
Regards,
Timmy Brolin
Muhamad Ikhwan Ismail wrote:
Hi Timmy,
If you read my prev post, you would know why the padding is useless to
me.
To Simon,
Understandable. Well if someone has the same problem, and checks this
thread I guess he can always just bring it back up.
PowerPC is more robust in big endian mode, it even corrects the
misalignment in big endian mode internallly (hardware). Why and how
to be honest I dont know (barely had any training on PowerPC, learned
all through books.)
There are certain PowerPC assembler intructions that cause problems in
little endian mode, I dont remember them by hard, need
to check the book.
Though you are correct about my method of correcting the problem would
make lwip slower :
1. My driver didnt have to copy the received buffer at all. So I spare
a lot there.
2. Fixing alignment in little endian mode is a very2 long
process/routine.
3. And I dont have to copy the header everytime. E.g in TCP I only had
to copy the header once for the multiple header processing.
So I hope this brings the end to the thread, at least till someone
might need something out of it. I am thankful that so many people
had tried to help.
Greetings,
Ikhwan
> Date: Sat, 24 May 2008 22:28:38 +0200
> From: address@hidden
> To: address@hidden
> Subject: Re: [lwip-users] Misalignment problems on PowerPC (little
endian mode)
>
>
> >> I have the source which can be compiled if the option
> >> LWIP_MISALIGNMENT is set to 1. If anyone interested and
have the same
> >> problem, I am more than willing to share and help. If you
guys want
> >> to incorporate it to lwip as alternative solution to
structure
> >> packing I am glad I can help. This lowers the stack
performance a bit
> >> though.
> >
> >
> > Not to offend you, but personally, I see this as a bug in the
compiler
> > you are using and we don't support broken compilers:
structure packing
> > _is_ a must for lwIP!
> >
> > Hope you are still having fun with lwIP!
> >
> > Simon
> >
> Actually, no. Structure packing is not necessarily a must for lwip.
> In many cases lwip should work just fine without structure
packing. I
> know that Texas Instruments DSP compilers will work with lwip
without
> structure packing.
> Patches made to lwip several years ago ensured that if
ETH_PAD_SIZE is
> set to 2, then no variable will ever be unaligned. This solves
most of
> the problems which would otherwise require structure packing.
>
> There are two things a compiler may do which will still mess up
the lwip
> structs:
> 1: Some compilers pad the size of all structs so that the size of
a
> struct becomes a multiple of 4.
> 2: Some comiplers put all structs on an address boundary of 4,
> regardless of the actual boundary requirements of the members of
the struct.
> Compilers which does any of the above would still require packed
> structs. Compilers which does neither of the above should work
without
> packed structs, if ETH_PAD_SIZE is set to 2.
>
> Regards,
> Timmy Brolin
>
>
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