Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[Jan Menzel]

On 30.11.2017 15:58, goldsimon wrote:
> 
> 
> Jan Menzel wrote:
>> I'd suggest to align (position and size) all receive
>> buffers to d-cache lines so that invalidation does not cause any side
>> effects.
> 
> And it's exactly this that lwip does not fully support yet. It doesn't work 
> for the tx side at all and for the rx side, we only have the workaraound with 
> custom pbufs (see the link Dirk posted).
> 
For TX there is nothing really needed on the LWIP side. Draining the
d-cache is always possible without side effects. Its just a question of
efficiently if a packet content does not start at a cache line.
        For RX the Ethernet data part has to be aligned to cache line to void
issues due to cache invalidation.
        In my implementations I use pooled memory. From the lwip code I can
see, that LWIP_MEM_ALIGN_SIZE() is used to add padding between
management data and actual free space. If this Macro is used to force
cache-line alignment, it would be already possible to use zero-copy RX
with cache. I can't see if custom pools are padded using the same macro,
but selecting an aligned size is not that difficult.
        (yes, the driver developer would have to add a few asserts to assure
the buffer used for rx is ready d-cache aligned)

        Jan