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Re: GNU Make enhansment patch - batching compiles
From: |
Jason Wessel |
Subject: |
Re: GNU Make enhansment patch - batching compiles |
Date: |
Thu, 3 May 2001 10:47:35 -0500 |
Here is a more concrete example and why $? doesn't work for this
application.
First the non-complicated example, with just single compiles:
all: 1.o 2.o 3.o
1.o: 1.c
gcc -c $<
2.o: 2.c
gcc -c $<
3.o: 3.c
gcc -c $<
Now if I want to batch up all the files to compiler at once
I try this to make use of the $?:
all: 1.o 2.o 3.o
1.o 2.o 3.o: 1.c 2.c 3.c
gcc -c $?
The problem here though is if you remove a single .o, or
a single .o fails to build. All the files get recompiled every time.
$? was designed for archives, not batch compiles.
Now for the batch way with the patch I am proposing:
all: 1.o 2.o 3.o batchbuild
1.o: 1.c
$(globalvar targlist,${targlist} $<)
2.o: 2.c
$(globalvar targlist,${targlist} $<)
3.o: 3.c
$(globalvar targlist,${targlist} $<)
batchbuild:
@if [ "${targlist}" = "" ] ; then\
echo "Targets up to date.";\
else\
echo ***building***: Batched ${targlist};\
gcc -c ${targlist};\
fi
As a side note, Paul was right with respect to the approach
to create a poor man's method to doing this. I didn't want
to spawn external processes or scribble temp files though.
The dependency evaluation runs much faster this way :-)
----- Original Message -----
From: "Eli Zaretskii" <address@hidden>
To: "Jason Wessel" <address@hidden>
Cc: <address@hidden>; <address@hidden>; <address@hidden>
Sent: Thursday, May 03, 2001 10:25 AM
Subject: Re: GNU Make enhansment patch - batching compiles
>
> On Thu, 3 May 2001, Jason Wessel wrote:
>
> > I needed the ability to change a variable from
> > inside the command section of a rule. Doing
> > this allows me to build a list of files that need
> > to be compiled, instead of passing the files to
> > the compiler one at a time. We have a program
> > that builds the make files already. The idea is
> > to feed the compiler multiple source files at the
> > same time.
>
> I'm confused: I don't understand how would you like this to work in
> practice (yes, I looked at the Makefile you attached, but I still cannot
> figure it out).
>
> First, how do you figure out which files need to be compiled and which
> don't? If this is based on the files' time stamps only, then the Make
> macro $? should allow you to do that without any extra features.
>
> If that somehow isn't enough, it should be possible to have Make include
> a file with the list of files that need to be recompiled. You could then
> have a special rule which generates that file as the first step of the
> build process. Something similar to what is explained in the manual
> about makedepend rules.
>