Re: add a Verilog HDL syntax highlighting file

[Jorge Juan]

El vie, 8 ene 2021 a las 17:34, Benno Schulenberg
(<bensberg@telfort.nl>) escribió:
>
>
> Op 07-01-2021 om 19:29 schreef Jorge Juan:
> > El jue, 7 ene 2021 a las 11:12, Benno Schulenberg (<bensberg@telfort.nl>)
> > escribió:
> >> However, the "rule" for including a syntax into nano is that the files that
> >> the syntax is for can be found on an average GNU/Linux install. Verilog
> >> files are not among those.
> >
> > All these tools are native GNU/Linux tools and can be found pre-packaged in
> > the most popular GNU/Linux distributions.
>
> What distro do you use?  Please provide links to the relevant packages in
> that distro, similar to this URL: https://packages.debian.org/sid/nano .

I use Debian and Ubuntu. At least Icarus Verilog has been in
Debian/Ubuntu for more than a decade. The three packages I have
mentioned are also standard in Fedora so I guess they come
pre-packaged in pretty much 99% of today's GNU/Linux distributions.

https://packages.debian.org/sid/iverilog
https://packages.debian.org/sid/verilator
https://packages.debian.org/sid/yosys
https://pkgs.org/search/?q=iverilog
https://pkgs.org/search/?q=verilator
https://pkgs.org/search/?q=yosys
>
> > An average GNU/Linux install for a hardware developer (most CS students take
> > a course on Verilog or VHDL design at some point) will include a Verilog
> > simulator,
>
> Especially students of computer science should be perfectly able to download
> a syntax file from some web page and install it to color up their editing of
> Verilog files.  No need to burden a default nano install with such a syntax.
>
I agree, they should :) In my experience, my first year CS students
are as good as configuring terminal text editors as any other student
of a technical/science degree.

> Wouldn't it make more sense to include a Verilog syntax file for nano with
> some major Verilog package?  Similar to what conky does:
>
> https://fedora.pkgs.org/rawhide/fedora-x86_64/conky-1.11.6-1.fc33.x86_64.rpm.html
>
I do not think it can be compared. Would you expect ruby, python or
gcc include syntax highlighting configuration for many text editors?
Conky syntax looks like a very specific case. (System)Verilog has been
an industry standard for more than 40 year and an international IEEE
Standard since 1995. It is a mainstream hardware description language
together with VHDL, as C, C++ or Python are in software.

> Or publish it on some wiki that many Verilog users visit?  As for Octave:
>
> https://wiki.octave.org/Nano
>
> > while the same CS students will probably never need syntax
> > highlighting for groff, email or ocaml, all included by default with nano.
>
> Those syntaxes were there before I became maintainer.

I see your point.
>
> > I think the syntax configuration I propose is much cleaner and richer than
> > the previously proposed in Savannah, which is more a work-in-progress
> > proposal.
>
> Understood.

I do not usually edit Verilog code with nano but I use nano frequently
to edit any kind of code when there is a good reason to use a terminal
(eg. over an ssh connection). It was nice to see that nano supported
syntax highlighting. I was trying to show my students how the could
write and simulate Verilog code even in an Android phone using Termux,
Icarus Verilog and nano [1]. I finally switched to vim because of the
syntax highlighting possibility.

[1] 
https://www.youtube.com/watch?v=qyLod1IIn1A&list=PLYqyVyA9IJnxgf3-ANm2OaSaLjj_aJVdw&index=4&t=730s

I understand that you may find Verilog not interesting enough to be
included with nano. It is ok. I will probably publish the syntax as a
gitlab snippet so it can be easily reached by interested users. In the
meantime, I decided to rework the syntax file a bit more and I have a
new version now supporting both Verilog and SystemVerilog. This time I
used the standard as a reference so I think it is much more complete
and useful right now. I include the new patch.

In this version I use very long regular expressions to match the whole
list of standard keywords. It make very long lines, which I do not
really like, but it is easier to maintain and probably more efficient
to parse.

Thanks you for your attention.

Jorge.


-- 
Jorge Juan

0001-Add-Verilog-HDL-syntax-highlighting.patch
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