Re: [Qemu-arm] [PATCH 00/18] Fix exception handling and msr/mrs access

[Peter Maydell]

On 9 November 2015 at 01:11, Michael Davidsaver <address@hidden> wrote:
> This series grew from a previous incorrect patch attempting to fix
> some incorrect behavior.  After spending some time going through the
> arch. ref. manual for v7-M I think I understand better how this should
> work and have made a number of changes which actually improve the situation.
>
> These changes have not yet been cross checked against real hardware, and
> I therefore don't consider them mergeable.  It's gotten big enough though
> that I'd like to get some feedback.

Thanks for this -- our M profile code has been in need of some love
for quite a while now.

> This series removes the dependence of the NVIC code on the GIC.  The GIC
> doesn't have the concept of PRIGROUP to change the size of the group
> priority field.  Also, there are a lot of cases in this code which
> I don't understand and worry about breaking.  Now that I have things
> working (I think), I could look at recombining them if this is desired.

I think separating out the NVIC is the right thing. Some of the
programmer-visible register views are superficially similar to the GIC,
but the underlying logic of how exceptions are dealt with is definitely
different, and trying to share code just makes it harder to maintain
both. (In particular for M profile external interrupts are just another
kind of exception and get prioritised along with all the internal
exceptions; for A/R profile the GIC really is an external thing
that prioritises external interrupts only to forward to the CPU.)

> I looked briefly at qtest, but can't quite see how to use it given
> the need to execute code to test most of the exception behavior.
>  Is something like this feasible at present?

You're correct that we don't have a very good story for how to test
parts of the system that really need execution of guest code.

I'll reply to the various patches individually with comments.

thanks
-- PMM