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[Qemu-arm] [PATCH v3 05/19] cpu: Add new asidx_from_attrs() method
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH v3 05/19] cpu: Add new asidx_from_attrs() method |
Date: |
Thu, 14 Jan 2016 13:52:41 +0000 |
Add a new method to CPUClass which the memory system core can
use to obtain the correct address space index to use for a memory
access with a given set of transaction attributes, together
with the wrapper function cpu_asidx_from_attrs() which implements
the default behaviour ("always use asidx 0") for CPU classes
which don't provide the method.
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
---
include/qom/cpu.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 58605a5..ed23246 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -102,6 +102,8 @@ struct TranslationBlock;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @debug_excp_handler: Callback for handling debug exceptions.
@@ -158,6 +160,7 @@ typedef struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
void (*debug_excp_handler)(CPUState *cpu);
@@ -492,6 +495,23 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState
*cpu, vaddr addr)
return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
}
+
+/** cpu_asidx_from_attrs:
+ * @cpu: CPU
+ * @attrs: memory transaction attributes
+ *
+ * Returns the address space index specifying the CPU AddressSpace
+ * to use for a memory access with the given transaction attributes.
+ */
+static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->asidx_from_attrs) {
+ return cc->asidx_from_attrs(cpu, attrs);
+ }
+ return 0;
+}
#endif
/**
--
1.9.1
- [Qemu-arm] [PATCH v3 06/19] cputlb.c: Use correct address space when looking up MemoryRegionSection, (continued)
- [Qemu-arm] [PATCH v3 06/19] cputlb.c: Use correct address space when looking up MemoryRegionSection, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 12/19] qom/cpu: Add MemoryRegion property, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 18/19] hw/arm/virt: add secure memory region and UART, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 01/19] exec.c: Don't set cpu->as until cpu_address_space_init, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 15/19] target-arm: Implement cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 09/19] exec.c: Use cpu_get_phys_page_attrs_debug, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 13/19] target-arm: Add QOM property for Secure memory region, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 08/19] exec.c: Add cpu_get_address_space(), Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 04/19] cpu: Add new get_phys_page_attrs_debug() method, Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 05/19] cpu: Add new asidx_from_attrs() method,
Peter Maydell <=
- [Qemu-arm] [PATCH v3 11/19] memory: Add address_space_init_shareable(), Peter Maydell, 2016/01/14
- [Qemu-arm] [PATCH v3 16/19] target-arm: Support multiple address spaces in page table walks, Peter Maydell, 2016/01/14