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[Qemu-arm] MPIDR Aff0 question

From: Andrew Jones
Subject: [Qemu-arm] MPIDR Aff0 question
Date: Thu, 4 Feb 2016 19:38:01 +0100
User-agent: Mutt/ (2014-03-12)

Hi Marc and Andre,

I completely understand why reset_mpidr() limits Aff0 to 16, thanks
to Andre's nice comment about ICC_SGIxR. Now, here's my question;
it seems that the Cortex-A{53,57,72} manuals want to further limit
Aff0 to 4, going so far as to say bits 7:2 are RES0. I'm looking
at userspace dictating the MPIDR for KVM. QEMU tries to model the
A57 right now, so to be true to the manual, Aff0 should only address
four PEs, but that would generate a higher trap cost for SGI broadcasts
when using KVM. Sigh... what to do?

Additionally I'm looking at adding support to represent more complex
topologies in the guest MPIDR (sockets/cores/threads). I see Linux
currently expects Aff2:socket, Aff1:core, Aff0:thread when threads
are in use, and Aff1:socket, Aff0:core, when they're not. Assuming
there are never more than 4 threads to a core makes the first
expectation fine, but the second one would easily blow the 2 Aff0
bits alloted, and maybe even a 4 Aff0 bit allotment.

So my current thinking is that always using Aff2:socket, Aff1:cluster,
Aff0:core (no threads allowed) would be nice for KVM, and allowing up
to 16 cores to be addressed in Aff0. As it seems there's no standard
for MPIDR, then that could be the KVM guest "standard".

TCG note: I suppose threads could be allowed there, using
Aff2:socket, Aff1:core, Aff0:thread (no more than 4 threads)


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