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Re: [Qemu-arm] [PATCH 3/6] target-arm: Implement MDCR_EL3.TDOSA and MDCR
From: |
Sergey Fedorov |
Subject: |
Re: [Qemu-arm] [PATCH 3/6] target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps |
Date: |
Mon, 8 Feb 2016 18:49:58 +0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 |
On 05.02.2016 19:45, Peter Maydell wrote:
> Implement the traps to EL2 and EL3 controlled by the bits
> MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap
> accesses to the "powerdown debug" registers.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
> ---
> target-arm/cpu.h | 12 ++++++++++++
> target-arm/helper.c | 23 ++++++++++++++++++++++-
> 2 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 80391fa..d1d6886 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -595,6 +595,18 @@ void pmccntr_sync(CPUARMState *env);
> #define CPTR_TTA (1U << 20)
> #define CPTR_TFP (1U << 10)
>
> +#define MDCR_EPMAD (1U << 21)
> +#define MDCR_EDAD (1U << 20)
> +#define MDCR_SPME (1U << 17)
> +#define MDCR_SDD (1U << 16)
> +#define MDCR_TDRA (1U << 11)
> +#define MDCR_TDOSA (1U << 10)
> +#define MDCR_TDA (1U << 9)
> +#define MDCR_TDE (1U << 8)
> +#define MDCR_HPME (1U << 7)
> +#define MDCR_TPM (1U << 6)
> +#define MDCR_TPMCR (1U << 5)
> +
> #define CPSR_M (0x1fU)
> #define CPSR_T (1U << 5)
> #define CPSR_F (1U << 6)
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 082701a..18e85fd 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -384,6 +384,24 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState
> *env,
> return CP_ACCESS_TRAP_UNCATEGORIZED;
> }
>
> +/* Check for traps to "powerdown debug" registers, which are controlled
> + * by MDCR.TDOSA
> + */
> +static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
> + bool isread)
> +{
> + int el = arm_current_el(env);
> +
> + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
> + && !arm_is_secure_below_el3(env)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
> + return CP_ACCESS_TRAP_EL3;
> + }
> + return CP_ACCESS_OK;
> +}
> +
> static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
> value)
> {
> ARMCPU *cpu = arm_env_get_cpu(env);
> @@ -3779,15 +3797,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
> { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
> .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
> .access = PL1_W, .type = ARM_CP_NO_RAW,
> + .accessfn = access_tdosa,
> .writefn = oslar_write },
> { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
> .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
> .access = PL1_R, .resetvalue = 10,
> + .accessfn = access_tdosa,
> .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
> /* Dummy OSDLR_EL1: 32-bit Linux will read this */
> { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
> .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
> - .access = PL1_RW, .type = ARM_CP_NOP },
> + .access = PL1_RW, .accessfn = access_tdosa,
> + .type = ARM_CP_NOP },
> /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
> * implement vector catch debug events yet.
> */
- [Qemu-arm] [PATCH 0/6] target-arm: Implement various EL3 traps, Peter Maydell, 2016/02/05
- [Qemu-arm] [PATCH 4/6] target-arm: Implement MDCR_EL2.TDRA traps, Peter Maydell, 2016/02/05
- [Qemu-arm] [PATCH 3/6] target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps, Peter Maydell, 2016/02/05
- Re: [Qemu-arm] [PATCH 3/6] target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps,
Sergey Fedorov <=
- [Qemu-arm] [PATCH 6/6] target-arm: Report correct syndrome for FPEXC32_EL2 traps, Peter Maydell, 2016/02/05
- [Qemu-arm] [PATCH 1/6] target-arm: correct CNTFRQ access rights, Peter Maydell, 2016/02/05