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Re: [Qemu-arm] [PATCH] target-arm: Implement MRS (banked) and MSR (banke
Re: [Qemu-arm] [PATCH] target-arm: Implement MRS (banked) and MSR (banked) instructions
Mon, 29 Feb 2016 19:24:25 +0300
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On 29.02.2016 19:18, Peter Maydell wrote:
> Starting with the ARMv7 Virtualization Extensions, the A32 and T32
> instruction sets provide instructions "MSR (banked)" and "MRS
> (banked)" which can be used to access registers for a mode other
> than the current one:
> * R<m>_<mode>
> * ELR_hyp
> * SPSR_<mode>
> Implement the missing instructions.
Likely, there is no disassembling support in QEMU for these instructions
as well. Are you going to add it?
> Signed-off-by: Peter Maydell <address@hidden>
> We don't support EL2 yet, but you can get at these on a v8 CPU in
> 32-bit EL1 if EL3 is enabled. Obviously there's not going to be much
> 32-bit EL1 code out there that uses the insns though, as it wouldn't
> work on v7 if it did...