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[Qemu-arm] [PATCH 03/23] target-arm: Define new arm_is_el3_or_mon() func
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 03/23] target-arm: Define new arm_is_el3_or_mon() function |
Date: |
Mon, 9 May 2016 18:29:29 +0100 |
The GICv3 system registers need to know if the CPU is AArch64
in EL3 or AArch32 in Monitor mode. This happens to be the first
part of the check for arm_is_secure(), so factor it out into a
new arm_is_el3_or_mon() function that the GIC can also use.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 066ff67..6ffc13b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -960,8 +960,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
}
}
-/* Return true if the processor is in secure state */
-static inline bool arm_is_secure(CPUARMState *env)
+/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
+static bool arm_is_el3_or_mon(CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_EL3)) {
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
@@ -973,6 +973,15 @@ static inline bool arm_is_secure(CPUARMState *env)
return true;
}
}
+ return false;
+}
+
+/* Return true if the processor is in secure state */
+static inline bool arm_is_secure(CPUARMState *env)
+{
+ if (arm_is_el3_or_mon(env)) {
+ return true;
+ }
return arm_is_secure_below_el3(env);
}
--
1.9.1
- [Qemu-arm] [PATCH 22/23] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes, (continued)
- [Qemu-arm] [PATCH 22/23] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming interrupts are group 1, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 20/23] target-arm/monitor.c: Advertise emulated GICv3 in capabilities, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 19/23] target-arm/machine.c: Allow user to request GICv3 emulation, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 23/23] RFC: hw/intc/arm_gicv3_kvm: Implement get/put functions, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 13/23] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 17/23] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 18/23] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 16/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_update(), Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 14/23] hw/intc/arm_gicv3: Implement gicv3_set_irq(), Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 03/23] target-arm: Define new arm_is_el3_or_mon() function,
Peter Maydell <=
- [Qemu-arm] [PATCH 01/23] migration: Define VMSTATE_UINT64_2DARRAY, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 02/23] bitops.h: Implement half-shuffle and half-unshuffle ops, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 15/23] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 04/23] target-arm: Provide hook to tell GICv3 about changes of security state, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 12/23] hw/intc/arm_gicv3: Implement GICv3 redistributor registers, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 07/23] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 05/23] target-arm: Add mp-affinity property for ARM CPU class, Peter Maydell, 2016/05/09
- [Qemu-arm] [PATCH 11/23] hw/intc/arm_gicv3: Implement GICv3 distributor registers, Peter Maydell, 2016/05/09