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Re: [Qemu-arm] [Qemu-devel] [kvm-unit-tests PATCH v2 00/10] arm/arm64: a

From: Andrew Jones
Subject: Re: [Qemu-arm] [Qemu-devel] [kvm-unit-tests PATCH v2 00/10] arm/arm64: add gic framework
Date: Wed, 8 Jun 2016 12:00:34 +0200
User-agent: Mutt/ (2014-03-12)

On Tue, Jun 07, 2016 at 06:13:53PM +0100, Alex Bennée wrote:
> Alex Bennée <address@hidden> writes:
> > Andrew Jones <address@hidden> writes:
> >
> >> v2:
> >>  Rebased on on latest master + my "populate argv[0]" series (will
> >>  send a REPOST for that shortly. Additionally a few patches got
> >>  fixes/features;
> >>  07/10 got same fix as kernel 7c9b973061 "irqchip/gic-v3: Configure
> >>        all interrupts as non-secure Group-1" in order to continue
> >>        working over TCG, as the gicv3 code for TCG removed a hack
> >>        it had there to make Linux happy.
> >>  08/10 added more output for when things fail (if they fail)
> >>  09/10 switched gicv3 broadcast implementation to using IRM. This
> >>        found a bug in a recent (but not tip) kernel, which I was
> >>        about to fix, but then I saw MarcZ beat me to it.
> >>  10/10 actually check that the input irq is the received irq
> >
> > Cool stuff. I'll get to reviewing this next week as my kvm-unit-tests
> > queue is getting overly long I need to clean-up and re-submit.
> OK I think I'm done for now. Sorry I've skipped the main bits of the GIC
> test but I'm not up to speed on the GIC layout so I'll defer to people
> who have a better understanding of it ;-)

OK, thanks for the review! May I ask that you also give it some testing?
I'd like some results for, at least, ACCEL=kvm,HOST=arm32 (which will
only be gicv2). I've already tested

x86_64  arm32   gicv2   tcg
x86_64  arm32   gicv3   tcg
x86_64  arm64   gicv2   tcg
x86_64  arm64   gicv3   tcg
arm64   arm32   gicv2   kvm, -cpu host,aarch64=off      (mustang)
arm64   arm64   gicv2   kvm, -cpu host                  (mustang)
arm64   arm64   gicv3   kvm, -cpu host                  (thunderx)

(Note, the gicv3 broadcast test with ACCEL=kvm will fail, unless
 you have a host kernel with dd5f1b049 "irqchip/gic-v3: Fix
 ICC_SGI1R_EL1.INTID decoding mask")


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